Speaker
Description
The lpGBT is a radiation-tolerant ASIC enabling high-speed optical communication for high-energy physics experiments. To address prototyping challenges in the designs, which include the lpGBT, we present an FMC mezzanine board and the lpGBT Stream IP Core. The mezzanine provides access to eLinks, clocks, GPIOs and configuration interfaces of lpGBT, allowing prototyping without a need for a custom PCB design. The developed IP core offers configurable eLink handling, AXI Stream/Lite interfaces, and built-in testing features for the eLinks. The both presented parts: mezzanine schematics and the IP core are open source and accompanied by detailed documentation.
Summary (500 words)
Our contribution addresses a practical bottleneck in prototyping detector readout systems, which plan using the lpGBT (Low-Power Gigabit Transceiver) ASIC.
During the development phase it can be difficult to integrate the lpGBT chip quickly. Its 289-pin BGA package with 0.5 mm pitch and high-speed signal integrity requirements can make the development of the PCB rather challenging, which may result in a significant delay before the firmware can run on the hardware. Another aspect, which may be challenging for the developer is implementing the firmware, providing the interface between the detector's front-end logic and the lpGBT chip. To help overcoming these implementation gaps our group has developed an FPGA Mezzanine Card (FMC) compliant with the VITA 57.1 standard, as well as a dedicated firmware solution, the “lpGBT Stream IP Core”. This combination significantly eases prototyping with the lpGBT chip.
Key specifications of the lpGBT mezzanine include:
- Breakout of 24 uplink eLinks and 2 downlink eLinks
- Access to the recovered clocks, GPIOs, ADC/DAC pins of the lpGBT chip
- Configurable lpGBT modes via hardware switches
- Access to the lpGBT chips internal registers via I2C
The “lpGBT Stream IP Core” provides:
- Configurable number of eLinks (up/down)
- AXI Stream interfaces for the detector data and controls (slave for uplink, master for downlink) -see the attached diagramm
- AXI Lite control registers
- Built-in test pattern generators for testing and phase-alignment training of the eLinks
As a demonstration of the functionality of the developed mezzanine and the IP-Core, we have implemented a detector setup , which binds a customly developed scintillating strips detector with SiPMs in a test-backend of the CMS-like Drift Tube readout electronics, which is autonomously operating in Aachen. The goal was a time-synchronized operation across heterogeneous detectors. The contribution will demonstrate successful synchronization between the two detector systems, showing spatial matching of the cosmic muon tracks after applying a timing coincidence requirement between the two detectors.
The work provides a complete, reusable prototyping ecosystem (hardware + firmware) that significantly reduces development time for lpGBT-based systems, making it highly relevant for ongoing and future high-energy physics instrumentation efforts. Both the schematics of the lpGBT mezzanine and the firmware of the "lpGBT Stream IP Core" are open-source, with the IP Core accompanied by detailed documentation.