Speaker
Description
We present the front-end readout electronics for the LHCb ECAL Phase-II
upgrade during LS4. The current ECAL will be replaced by PicoCal, designed to sustain higher pile-up, occupancy, and radiation levels with a five-fold increase in granularity across regions with different technologies. PicoCal targets a timing resolution below \SI{15}{ps} over \SI{50}{MeV} to \SI{5}{GeV}, with channel occupancy up to \SI{30}{\percent}. The readout is based on a new 64-channel FEB integrating two custom ASICs: ICECAL65 for energy and SPIDER for timing, alongside radiation-hard CERN components lpGBT, VTRx$^{+}$, and bPOL. 350 boards will be produced for installation in 24 crates.
Summary (500 words)
The current ECAL will require a major upgrade to sustain higher pile-up, occupancy, and radiation doses. The total number of channels will be multiplied by $5$. Time measurement with precision below \SI{15}{ps} rms in a range of \SI{50}{MeV} to \SI{5}{GeV} is required to mitigate pile-up events. A significant redesign is foreseen during Long Shutdown 4; the upgraded detector is known as PicoCal. Maximum channel occupancy is \SI{30}{\percent} at \SI{12}{Mevent/s}. The electronics must withstand a total ionizing dose of \SI{20}{krad} at the end of Run 5 [1,2].
We will present the front-end readout electronics designed for the LHCb Upgrade II. We will describe the full readout chain, clock distribution from the backend to each board, and the FEB design, which integrates two ASICs for energy and timing.
$350$ new FEBs will be produced, each reading $64$ channels housed in $24$ crates. The signal from each photomultiplier tube passes through a $3$-gain PAC signal conditioner and splits into three parallel paths. Two paths feed the ICECAL65 [3]. The timing path feeds SPIDER [4].
Both ASICs are designed in TSMC CMOS \SI{65}{nm}. ICECAL65 runs at \SI{1.28}{Gb/s} per block. SPIDER includes a dedicated serial link at \SI{2.56}{Gb/s} per channel. Eight channels per block are hosted per FEB. Data compression is applied before transmission to the lpGBT.
A Microchip PolarFire FPGA handles signal processing, timing extraction, data compression, and merges both streams at $224$ bits at \SI{40}{MHz}. A Master PolarFire is considered to handle slow control, monitoring, and calibration via USB/Ethernet. The lpGBT [5] receives data from the FPGA via e-links and transmits to the DAQ via VTRx+ at \SI{10}{Gbps} [6]. The lpGBT also distributes the LHC clock to each ASIC. Power is supplied at \SI{12}{V}, stepped down by a bPOL DC-DC converter [7].
SPIDER is based on the Waveform Time-to-Digital Converter [4] principle, formerly introduced by the SAMPIC ASIC [8]. It captures the full signal waveform within periodic time windows phase-locked to the \SI{40}{MHz} LHC clock. Start and stop times are adjustable in steps of \SI{195}{ps}. A recording depth of $32$ samples per channel is sufficient. Each channel houses $8$ banks of $32$ analog memory cells. Conversion uses a massively parallel Wilkinson ADC at \SI{5}{GHz} over $10$ bits with a maximum conversion time of \SI{200}{ns}. The sampling frequency is configurable between \SI{1.6}{GS/s} and \SI{20}{GS/s}. Time reconstruction applies a constant-fraction discriminator algorithm to the digitized waveform. The first prototype achieved a single-channel time resolution of \SI{5}{ps} rms, which is below the \SI{15}{ps} rms required for the full chain.
ICECAL65 is the successor of ICECAL [3], which is already deployed in the current calorimeter. ICECAL65 uses a time-interleaved scheme, two subchannels alternating every \SI{25}{ns} with no dead time. Dynamic range is \SI{1}{V}, dual-gain, $11$-bit resolution, below \SI{50}{mW} per channel. The $4$-channel prototype V0 has been submitted. The $8$-channel version with on-chip ADC, V1, is the final production version.