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Description
SHINE is a hard X-ray free electron laser device with pulse repetition rates up to 1 MHz, requiring high-speed pixel detectors such as STARLIGHT with target frame rates higher than 10 kHz . In order to meet its high data transmission requirements while enabling portable detector testing, this work developed a firmware architecture based on TB5. This design integrates power transmission, detector configuration and image data transmission into a single high-speed link. This work providing a practical basis for future module-level readouts, portable deployments, and laptop-based debugging.
Summary (500 words)
A high speed readout scheme of STARLIGHT pixel detector based on USB Thunderbolt 5 (TB 5) is proposed in this work. SHINE is a hard X-ray free electron laser device with pulse repetition rate up to 1 MHz. STARLIGHT is a detector suitable for SHINE, with target frame refresh rate up to 10 kHz and dynamic range up to 10^4, so its back-end readout system requires transmission bandwidth of tens of Gbit/s. The proposed TB5 architecture addresses this requirement while also improving portability and simplifying detector testing.
The system integrates power delivery, detector configuration, timing control, and image data transmission into a single high-speed TB5 link. The hardware path connects the FPGA board to the host PC through onboard PCIe, a TB5 docking device, and a TB5 expansion interface. In the rate test, XDMA with BRAM was used as a stable FPGA-side data source, and the measured peak effective throughput reached 41 Gbps. This exceeds the 34 Gbps transmission requirement of a STARLIGHT single module, demonstrating that the TB5/PCIe path can support high-speed detector readout.
On the firmware side, a unified TB5/PCIe backend framework was developed. Host commands are received by the FPGA through the XDMA User BAR and distributed through the Wishbone bus to the register table, SPI controller, GPIO interface, timing logic, and power-board control. For data acquisition, ASIC output signals are captured through GPIO, aligned and deserialized by IDELAY/ISERDES, buffered in FIFO, and transferred to the PC through XDMA C2H and TB5.
The host-side software is implemented in MATLAB. It writes mapped control registers through xdma_rw.exe, loads GDAC configuration files, performs chip reset and working-mode setup, enables configuration, and then starts XDMA C2H readout. The received PCIe data are extracted from the valid lane, cut into the effective payload, decoded with an LFSR lookup table, and reconstructed into two-dimensional count and gain images.
In the final validation, an internal voltage calibration circuit was used as the source because no XFEL beamline was available. Sensorless noise data were successfully transferred, decoded, and reconstructed into a 2D spatial distribution map, confirming that the TB5-based firmware and host software can support practical detector configuration and readout.