Speaker
Description
The CMS Phase-2 High-Granularity Calorimeter (HGCAL) employs a high-bandwidth front-end with significant variations in topology and data rates. To support the back-end firmware development, an FPGA-based front-end emulator has been implemented on a Serenity-S1 FPGA board. The emulator framework uses lpGBT link emulation along with output buffer emulation of the key front-end ASICs. Additional features include controlled error injection, such as single-event upsets and burst errors, and the generation of edge-case conditions. This provides a scalable and versatile platform for larger-scale system-level testing in preparation for the upcoming cassette and sector tests for the HGCAL detector.
Summary (500 words)
The Phase-2 upgrade of the CMS experiment at the High-Luminosity LHC introduces the High-Granularity Calorimeter (HGCAL), a sampling calorimeter based on silicon sensors in high-radiation regions and scintillator tiles with SiPM readout in lower-radiation regions. Despite differing detector technologies, both systems share a common readout architecture based on the HGCROC ASIC for sensor readout, followed by the ECON-T and ECON-D concentrator ASICs for trigger and DAQ paths. Data are serialised via lpGBT links and transmitted through VTRx+ optical modules to the Serenity-S1 ATCA back-end boards. To accommodate the large variation in occupancy and data rates, the front-end is implemented in multiple configurations with differing numbers of HGCROC and ECON ASICs per lpGBT link and variations in the interconnection layout, resulting in non-uniform data streams at the back-end interface.
To support the development and validation of back-end firmware under realistic operational conditions, an FPGA-based front-end emulator framework has been developed and implemented on a Serenity-S1 FPGA board. The emulator reproduces the functional behaviour of the front-end data path, including lpGBT link emulation and lightweight models of the ECON-T and ECON-D ASICs, with emphasis on correct packet formatting, configurable traffic patterns, and deterministic data generation.
A central feature of the emulator is its flexibility in reproducing different front-end topologies. The emulator supports up to 124 simultaneous lpGBT instances, enabling emulation of a full load for a single back-end Serenity-S1 board, under configurable front-end configurations. Front-end topology, including lpGBT placement, ECON-D/-T aggregation, and link mapping, is defined through a lightweight configuration interface implemented in a VHDL package. This approach enables rapid switching between detector layouts without deeper architectural modifications, facilitating efficient exploration of system configurations during firmware development and integration.
In addition to topology flexibility, the emulator provides a controlled fault-injection infrastructure for system-level stress testing. It supports programmable injection of single-event upsets, burst errors, and data corruption scenarios at configurable locations in the data path. The framework can also generate edge-case conditions such as data rate fluctuations, high-energy-like payloads, and malformed packets. These features enable systematic validation of back-end robustness under conditions that are difficult or impractical to reproduce using physical front-end hardware alone.
By combining scalable and flexible topology emulation with configurable traffic generation and fault injection, the framework provides a practical environment for the validation of HGCAL back-end firmware and the preparation towards larger system tests as the HGCAL detector production ramps up.