Speakers
Description
This work presents the firmware architecture and implementation of the Barrel Calorimeter Processor (BCP) for the Phase-2 CMS ECAL Barrel as well as the ECAL refurbishment. The presentation focuses on a single Front-End Driver (FED), addressing resource allocation and key implementation challenges. System performance is validated through a slice test with five Very Front-End (VFE) boards and one Front-End (FE) board streaming raw data to the BCP. Following trigger reception, data are read out via the CMS DAQ and Timing Control Distribution System (DTH). Results confirm reliable synchronization and accurate ADC pedestal and test pulse readout, demonstrating robust firmware performance.
Summary (500 words)
The refurbishment of the Barrel region of the CMS Electromagnetic Calorimeter (ECAL) is scheduled to begin in 2027, as part of the preparations for the LHC Phase-2 upgrade. This effort includes the extraction of 36 Super Modules (SMs) and their transfer to the surface for replacement of on-detector electronics. Prior to reinstallation in the CMS cavern, the upgraded electronics must undergo comprehensive validation to ensure functionality, integrity, and reliable communication for long-term operation.
A key component of the upgraded system is the Barrel Calorimeter Processor (BCP), a Back-End ATCA blade shared between CMS ECAL and HCAL. The BCP provides clock and control distribution, raw data reception and decompression, trigger primitive generation, interfacing with the Level-1 trigger, and data readout. In the refurbishment phase, the trigger primitive-related functionalities are removed, allowing resources to be reallocated to increase data throughput. As a result, each BCP will service up to one-third of a Super Module, doubling its interface capacity with both the Front-End electronics and the Data Acquisition (DAQ) system.
The BCP is built around a Xilinx UltraScale+ XCVU13P FPGA, featuring Stacked Silicon Interconnect (SSI) technology and four Silicon Logic Regions (SLRs). This architecture imposes constraints on firmware design and floorplanning. The firmware is therefore partitioned across the four SLRs, with each region handling multiple Front-End (FE) inputs, up to twelve in the final system configuration and up to twenty-four during refurbishment, while collectively forming a four Front-End Driver (FED) in a single BCP. The presentation focuses on the test and performance of a single Front-End Driver (FED).
This contribution presents the firmware architecture and implementation developed for the CMS Phase-2 as well as operation during the refurbishment period, with emphasis on a single FED configuration. We discuss resource allocation, design challenges, and adopted solutions. System performance is demonstrated through a slice test, where five Very Front-End (VFE) boards and one FE board (corresponding to an ECAL tower) stream raw data to the BCP. Upon reception of a trigger, the data are read out via the CMS DAQ and Timing Control and Distribution System (TCDS) hub (DTH). We further present results on system synchronization, ADC pedestal readout, and test pulse validation from the VFE electronics.