Speaker
Description
Abstract
GETROC is a 36-channel front-end ASIC designed for Liquid Argon calorimeters in future high-energy physics experiments, with compatibility for Silicon detectors. Derived from the HGCROC architecture, it extends operation to cryogenic environments (77 K) and large detector capacitances. Each channel combines a low-noise front-end with dual-path digitisation, achieving a 10 pC dynamic range with better than 1% linearity. A trigger-less architecture with on-chip buffering and 1.28 Gbps links enables efficient data streaming. Cryogenic operation improves intrinsic noise but introduces constraints on power dissipation and reliability. The prototype, received in 2026, is under characterisation across temperature and dynamic range.
Summary
GETROC is a 36-channel system-on-chip designed as a versatile readout ASIC for both Silicon and Liquid Argon (LAr) calorimeters in future high-energy physics experiments. It builds on the proven HGCROC architecture while extending its operation to cryogenic environments and large detector capacitances, targeting applications such as the ALLEGRO detector at the Future Circular Collider. Unlike conventional front-end electronics located outside the active medium, GETROC is intended to operate directly inside LAr (77 K), reducing analog signal path length and feedthrough complexity, and benefiting from reduced intrinsic noise at cryogenic temperature, improving signal integrity through early digitisation. This strongly constrains power consumption and device reliability.
Each channel integrates a low-noise analog front-end followed by dual-path digitisation to cover a wide dynamic range up to 10 pC while maintaining linearity better than 1%. Small signals are processed by a 10-bit SAR ADC, while larger signals are handled by a 12-bit time-over-threshold TDC, providing an efficient trade-off between precision and dynamic range. Time-of-arrival is measured with a 10-bit TDC achieving a resolution better than 25 ps for input charges above 50 fC. This functionality is inherited from the HGCROC architecture and retained to evaluate its relevance in cryogenic calorimetry, where current physics requirements may not demand such precision.
A key feature of GETROC is its trigger-less (streaming) readout architecture, where events are selected locally based on signal thresholds. This removes the need for a global trigger and reduces dead time at high rates, but shifts complexity to on-chip data handling. The digital backend includes a 32-depth circular buffer with Hamming encoding for error protection, and zero suppression to limit bandwidth by transmitting only active channels. Data are output via two 1.28 Gbps serial links (18 channels each), matching expected hit rates while maintaining manageable power consumption.
The design faces several significant challenges. Operation over a wide temperature range (77 K to 40°C) affects transistor characteristics, timing stability, and analog performance. The front-end must accommodate detector capacitances up to 800 pF while achieving an equivalent noise charge below 2800 electrons, corresponding to roughly one-fifth of the signal from a minimum ionizing particle. While cryogenic operation improves intrinsic noise performance, it also requires careful control of digital switching noise and bias stability. The current power consumption is 10 mW per channel and must be reduced in future iterations to minimise the risk of local LAr boiling, requiring a balance between analog performance, high-speed serialization (1.28 Gbps), and clock generation.
Clock distribution and synchronization are handled by an on-chip PLL generating phase-adjustable frequencies (1.28 GHz, 160 MHz, 40 MHz), enabling precise timing alignment across channels. Configuration and control are provided via an I2C interface and a fast command system operating at 320 MHz.
The first prototype, implemented in a 130 nm CMOS process, was received in April 2026 and is under test across the full dynamic and temperature range. GETROC explores the feasibility of embedding complex, low-power, mixed-signal electronics directly in cryogenic detectors, balancing improved signal integrity against challenges in reliability, power dissipation, and system integration.
Summary (500 words)
CALOROC1C is a 36-channel system-on-chip designed as a versatile readout ASIC for both Silicon and Liquid Argon (LAr) calorimeters in future high-energy physics experiments. It builds on the proven HGCROC architecture while extending its operation to cryogenic environments and large detector capacitances, targeting applications such as the ALLEGRO detector at the Future Circular Collider. Unlike conventional front-end electronics located outside the active medium, CALOROC1C is intended to operate directly inside LAr (77 K), reducing analog signal path length and feedthrough complexity, and benefiting from reduced intrinsic noise at cryogenic temperature, improving signal integrity through early digitisation. This strongly constrains power consumption and device reliability.
Each channel integrates a low-noise analog front-end followed by dual-path digitisation to cover a wide dynamic range up to 10 pC while maintaining linearity better than 1%. Small signals are processed by a 10-bit SAR ADC, while larger signals are handled by a 12-bit time-over-threshold TDC, providing an efficient trade-off between precision and dynamic range. Time-of-arrival is measured with a 10-bit TDC achieving a resolution better than 25 ps for input charges above 50 fC. This functionality is inherited from the HGCROC architecture and retained to evaluate its relevance in cryogenic calorimetry, where current physics requirements may not demand such precision.
A key feature of CALOROC1C is its trigger-less (streaming) readout architecture, where events are selected locally based on signal thresholds. This removes the need for a global trigger and reduces dead time at high rates, but shifts complexity to on-chip data handling. The digital backend includes a 32-depth circular buffer with Hamming encoding for error protection, and zero suppression to limit bandwidth by transmitting only active channels. Data are output via two 1.28 Gbps serial links (18 channels each), matching expected hit rates while maintaining manageable power consumption.
The design faces several significant challenges. Operation over a wide temperature range (77 K to 40°C) affects transistor characteristics, timing stability, and analog performance. The front-end must accommodate detector capacitances up to 800 pF while achieving an equivalent noise charge below 2800 electrons, corresponding to roughly one-fifth of the signal from a minimum ionizing particle. While cryogenic operation improves intrinsic noise performance, it also requires careful control of digital switching noise and bias stability. The current power consumption is 10 mW per channel and must be reduced in future iterations to minimise the risk of local LAr boiling, requiring a balance between analog performance, high-speed serialization (1.28 Gbps), and clock generation.
Clock distribution and synchronization are handled by an on-chip PLL generating phase-adjustable frequencies (1.28 GHz, 160 MHz, 40 MHz), enabling precise timing alignment across channels. Configuration and control are provided via an I2C interface and a fast command system operating at 320 MHz.
The first prototype, implemented in a 130 nm CMOS process, was received in April 2026 and is under test across the full dynamic and temperature range. CALOROC1C explores the feasibility of embedding complex, low-power, mixed-signal electronics directly in cryogenic detectors, balancing improved signal integrity against challenges in reliability, power dissipation, and system integration.