Speaker
Description
Abstract —
A mass-production tester was developed for the RPC DCT boards of the ATLAS Phase-II upgrade, covering both legacy BM/BO and new BI detector variants. The system validates complete board functionality during prototype, pre-production, and forthcoming production phases. It emulates the RPC Sector Logic interface and 288 front-end hit inputs using representative 1 MHz, 12.5 ns pulses. Tests include lpGBT communication, 10 Gb/s link eye scans, I2C, ADC, GPIO, PRBS7 E-Link validation, clock and configuration paths, FPGA programming through lpGBT GPIO-based JTAG emulation, and current monitoring. The tester standardizes quality control for reliable large-scale DCT production.
Summary (500 words)
Summary —
The RPC DCT boards are readout and trigger-interface boards developed for the ATLAS Phase-II upgrade. A total of 1570 DCT boards, including both BM/BO and BI variants, must be tested for the final system. The BM/BO boards serve the legacy RPC chambers, while the BI boards serve the new BI detectors. Both variants receive 288 front-end input channels but use different connector layouts and signal standards. The BM/BO DCT uses eight front-end connectors, while the BI DCT uses twelve. This requires a tester that can support both designs without compromising production throughput or duplicating the full test infrastructure.
A dedicated mass-production tester has been developed to validate each DCT board through prototype, pre-production, and production. The final system described here evolved from two smaller-scale testers previously used for DCT prototype validation. The tester emulates both the RPC Sector Logic interface and the front-end detector signals. For input validation, it generates representative 1 MHz hit pulses with 12.5 ns duration on all 288 channels. It also verifies lpGBT communication, including the 10 Gb/s optical link, 320 Mb/s E-Links using PRBS7 patterns, I2C, ADC, GPIO, clock distribution, configuration paths, and current consumption.
Several implementation challenges had to be addressed. The main tester board was designed as a reusable FPGA-based platform, combining a 10 Gb/s lpGBT SFP link, an additional 10 Gb/s QSFP interface, 1 Gb/s Ethernet, clock distribution for the FPGA fabric and GTH transceivers, power delivery and current monitoring, and routing of 72 differential pairs operating at 560 Mb/s to the mezzanine connectors. The mezzanines emulate two front-end electrical interfaces using custom level-conversion circuits for BM/BO negative-pulse signaling and BI open-collector differential signaling, while keeping the system modular and cost-constrained.
The implementation is completed by four dedicated FPGA firmware designs: BM/BO and BI versions for the tester FPGA, and corresponding BM/BO and BI test firmware for the DCT FPGA. These firmware designs implement the variant-specific test logic, including front-end signal emulation, lpGBT and E-Link validation, FPGA configuration through lpGBT GPIO-based JTAG emulation, and board-level diagnostic procedures. A PC application with a graphical user interface communicates with the tester through 1 Gb/s Ethernet and coordinates the full test sequence, from configuration and execution to result collection. For each tested board, the software also produces a result log for future reference. This provides a standardized and operator-friendly workflow for production quality control.