Speaker
Description
MOSAIX is a wafer‑scale Monolithic Active Pixel Sensor (MAPS) implemented in a 65 nm CMOS imaging process using stitching, with overall dimensions of 266×19.6 mm². It integrates all the functionalities required for the ALICE ITS3 Upgrade.
This contribution provides a retrospective view of the development and implementation of the MOSAIX chip. It focuses on implementation challenges arising from the unprecedented size, complexity, integration, and system‑level requirements of the device, and discusses methodologies and solutions adopted to address them. The aim is to highlight lessons learned that may be relevant for future developments.
Summary (500 words)
MOSAIX is a wafer‑scale Monolithic Active Pixel Sensor (MAPS) implemented in a 65 nm CMOS imaging process using stitching, with overall dimensions of 266 × 19.6 mm². While earlier developments demonstrated the feasibility of large‑area MAPS, MOSAIX was developed targeting the ALICE ITS3 upgrade and marks a transition toward a fully featured system‑on‑chip, integrating all functionalities required for ITS3.
This contribution provides a retrospective view of the development and implementation of the MOSAIX chip. It focuses on selected challenges arising from the unprecedented size, functional integration, and system‑level requirements of the device, and discusses the technical solutions and methodologies adopted to address them. The aim is to highlight lessons learned that may be relevant for future developments.
MOSAIX is composed of three main components: the Left Endcap (LEC, 4.5 × 19.6 mm²), hosting control and monitoring, data aggregation, and external interfaces; the Repeated Sensor Unit (RSU, 21.7 × 19.6 mm²), replicated twelve times; and the Right Endcap (REC, 4.5 × 19.6 mm²), providing additional power interconnects. The RSUs contain 144 independently powerable tiles, corresponding to 288 local supply domains. Each tile integrates a 444 × 156 pixel array (9.9 Mpixels total), biasing DACs, and a dedicated readout periphery. Each tile transmits data to the LEC at 160 Mbit/s over one of 144 on‑chip links up to 26 cm long, using a custom low‑swing differential scheme. The LEC aggregates data and implements Versatile Link+‑compatible encoders, interfacing to eight 10.24 Gbit/s serializers.
The high level of mixed‑signal integration increased integration risk. This was addressed through a hierarchical digital‑on‑top implementation flow supported by rigorous verification methodologies. Despite these measures, multiple refinement cycles could not be fully prevented. Accurate functional, timing, and power models of analog‑centric components were developed and employed during implementation and verification. Data transmission on‑chip at wafer scale required extensive analog simulations to account for on‑chip voltage variations across large distances.
Yield and manufacturability were central design drivers. Custom DFM rules, including increased wiring widths and spacings, were added to automated layout checks. Standard‑cell libraries were modified accordingly, and redundancy was employed in selected blocks. Fine‑grained power domain segmentation aimed to improve fault resilience: on‑chip switches allow tiles to be isolated in case of local shorts. This required extended power‑aware verification, including validation of power‑up and power‑down sequences.
Power distribution represented another key challenge. Strict consumption limits were set by allowable IR drops on limited metal resources and by the small number of external supply connections separated by 27 cm. Careful power budgeting was required, and despite a target power density of 40 mW/cm², a modification of the metal stack providing thicker metal layers was needed. Leakage reduction relied on custom low‑leakage logic for the pixel arrays and exclusion of extreme process and temperature corners. Extensive power‑integrity analyses were essential throughout design and sign‑off.