Speaker
Description
A primary challenge in High Energy Physics (HEP) data acquisition is the aggregation of numerous low-speed (10Gb/s) radiation-hard data links into high-speed back-end interfaces. While high-end FPGAs traditionally perform this task, transceiver density and speed in modern devices can limit cost-effective scaling. This study proposes a two-stage architecture that utilizes mid-range FPGAs for decoding and Ethernet conversion, followed by a Microchip META-DX2+ Ethernet PHY that aggregates these streams into a 400GbE interface. This study evaluates the design’s performance, validating it as a scalable and cost-effective architecture for next-generation HEP data acquisition systems.
Summary (500 words)
As Large Hadron Collider (LHC) experiments upgrade their detectors, the demand for high-speed data links is increasing significantly. Due to the high-radiation environments and stringent power constraints, low-speed, radiation-hardened transceivers and protocols must be employed, such as the 10 Gb/s Low-power GigaBit Transceiver (LpGBT). Currently, these non-standard links are received and aggregated in the back-end using expensive, high-end FPGAs before being processed by the Event Filter Farm. However, as modern high-end FPGAs move toward ultra-high-speed transceiver hardware, they are increasingly reducing the density and protocol support required for these slower, high-volume links.
This design presents a two-stage architecture that combines a mid-range FPGA, capable of interfacing with a large number of slower links, with a Microchip META-DX2+ Ethernet PHY. This PHY enables the implementation of 400 Gb/s Ethernet interfaces using 106G PAM4 signaling.
This study specifically focuses on evaluating the aggregation functionality of the META-DX2+. Front-end data is simulated using multiple synthetic UDP streams representing packetized LpGBT data; each stream limited at 10 Gb/s throughput with a fixed 4 KB packet size. These streams are aggregated in software into 100 Gb/s Ethernet streams, and this traffic generator is replicated three times to provide a total input throughput of 300 Gb/s to the META-DX2+.
The three 100 Gb/s Ethernet links are aggregated into a single 400 Gb/s interface with 106G PAM4 signaling using the PHY’s XpandIO feature. The integrity of the transmission and aggregation is verified using a traffic checker. In this first test, only a single slice of the two available in the PHY is selected. To further expand the capacity, the ASIC is configured using its ShiftIO feature, which enables the utilization of the remaining SerDes as input channels.
A second test validates this configuration, successfully aggregating six 100 Gb/s Ethernet interfaces into dual 400 Gb/s outputs. The study demonstrates that this two-stage architecture provides a viable and cost-effective solution for the high-density aggregation of custom readout links into standard high-speed Ethernet interfaces.