TWEPP26 Topical Workshop on Electronics for Particle Physics

Session

Systems

29 Sept 2026, 15:20

Castelldefels, Barcelona, Spain

9. Electronics front-end for diamond and SiPM detectors

Christophe Hoarau (LPSC/IN2P3/CNRS)

29/09/2026, 15:20

System - System Design, Description and Operation

Oral

This presentation focuses on the readout electronics for SiPMs and diamond detectors, for real-time monitoring of dose deposition in proton therapy. The principle of particle trajectory reconstruction relies on precise timing measurements, i.e. to achieve millimetre-scale resolution, measurements must be accurate to within 100 ps. To meet this requirement, we have developed 50 channels signal...

65. Mini Drift Tubes with triggerless readout for the upgrade of the SND@LHC muon system

Luigi Guiducci (Universita e INFN Bologna (IT))

29/09/2026, 15:40

System - System Design, Description and Operation

Oral

In March 2025 the muon system of the SND@LHC detector was upgraded with Mini Drift Tubes modules. The contribution will describe the new detectors, smaller versions of CMS Drift Tubes, and the electronics for the triggerless time-to-digital conversion and readout, based on the OBDT-theta board for the Phase2-upgrade of CMS Drift Tubes and on a VCU118 board as a backend system. The integration...

86. ARC: A Contract-Driven Framework for Automated Integration and Verification of Large-Scale FPGA Trigger Systems

Pelayo Leguina (Universidad de Oviedo (ES))

29/09/2026, 16:00

Logic - Digital Design, Verification Tools and Methods

Oral

Modern Level-1 trigger firmware for the HL-LHC integrates tens of HLS and RTL modules into fixed-latency FPGA pipelines, where manual wiring, latency alignment, and verification create major engineering risk. We present ARC (Algorithm Runtime and Contract framework), a plugin-agnostic, contract-driven toolchain that automates top-level RTL generation, static latency checking, and...

174. LHCb Mighty Tracker Electronics - Reading and controlling a hybrid MAPS and SciFi Tracker in LHC Run 5

Michael Lupberger (University of Freiburg (DE))

29/09/2026, 17:40

System - System Design, Description and Operation

Oral

Within LS4, the LHCb experiment will undergo its major Phase-IIb upgrade. The spectrometer's downstream SciFi tracker will be replaced by a hybrid detector designed to handle higher occupancies and radiation levels. The central high-occupancy regions will employ Monolithic Active Pixel Sensors, while the outer regions will use Scintillating Fibres read by cryogenically cooled Silicon...

84. Operation of SPECTRE CZT detector

Federico Matias Melendi (Universita e INFN, Ferrara (IT))

29/09/2026, 18:00

System - System Design, Description and Operation

Oral

The INFN SPECTRE (Single Photon Emission Computed Tomography Readout Electronics) project aims to design, assemble, and characterize a complete detection module based on CZT sensors for medical applications. For readout, SPECTRE uses the electronics developed for a high-capacitance gas detector (CGEM@BESIII, IHEP, Beijing): the TIGER (Torino Integrated GEM Electronics for Readout) ASIC for...

199. The CMS Barrel Muon Layer 1 System : Design, Integration Setups, and Commissioning Tools

Ignacio Redondo Fernandez (CIEMAT - Centro de Investigaciones Energéticas Medioambientales y Tec. (ES))

30/09/2026, 09:00

System - System Design, Description and Operation

Oral

The BMTL1 system is the trigger and readout backend of the CMS Barrel Muon during HL-LHC. 30 custom design ATCA bmtl1 boards generate station primitives running complex logic on VUP13 FPGAs using the full precision data sent by the upgraded frontend of the muon detector. A second layer of 12 bmtl1 boards aggregates wedges easing the transition to TMT-18 scheme used by next trigger layers. Its...

21. A Scalable Two-Stage Back-End Architecture for 400GbE Data Acquisition Systems

Alberto Perro (CERN)

30/09/2026, 09:20

System - System Design, Description and Operation

Oral

A primary challenge in High Energy Physics (HEP) data acquisition is the aggregation of numerous low-speed (10Gb/s) radiation-hard data links into high-speed back-end interfaces. While high-end FPGAs traditionally perform this task, transceiver density and speed in modern devices can limit cost-effective scaling. This study proposes a two-stage architecture that utilizes mid-range FPGAs for...

97. A Two-Tier Low Power Wireless Readout Cell Architecture for PEPS

Yifan Yang (Universite Libre de Bruxelles (BE))

30/09/2026, 09:40

System - System Design, Description and Operation

Oral

Scalable communication is needed for PEPS,a future gamma-ray array of 10
km2 with 55 solar-powered detector stations per km² at the Pierre Auger
Observatory. With the legacy access radio unavailable for PEPS, we propose a two-tier architecture: a 2.4 GHz FLRC fixed-slot first-hop layer from stations to a per-cell aggregation node, followed by 5 GHz backhaul to the DAQ. Separating access from...