Speaker
Description
The IGNITE project develops technical solutions for the next generation of trackers at colliders. The final ASIC, the IgnitER, is being designed to have pitch of 45 µm and time resolution on the full chain (sensor to TDC) below 50 ps.
We present measurements aimed at characterizing the Ignite64, a prototype featuring a matrix of 64x64 pixels and a pitch of 55 µm. Tests are made both with and without bonded 3D sensors. This results and detailed performance analysis are giving important hints for the completion of the IgnitER, whose design criteria, status, and expected performance will be also illustrated.
Summary (500 words)
The INFN IGNITE project is developing technical solutions in CMOS 28-nm technology for the next generation of trackers at colliders, which require high time resolution at the pixel level (<30 ps RMS on the electronic side), while keeping the pixel size (~50 µm) and system power consumption substantially unaltered with respect to the present generation of inner tracking systems (1 to 1.5 W/cm^2, considering the example of CMS/ATLAS-phase2 and LHCb Upgrade-1).
In this paper we present test results about a prototype ASIC, the Ignite64, featuring a matrix of 64x64 pixels, equipped with 1 TDC per pixel, and conceived to test prototype silicon sensors of 55 µm pitch, developed within the AIDAInnova initiative in recent years (such us 3D, TI-LGAD, i-LGAD etc.). The Ignite64 is designed according to a modular architectural concept which is being replicated in the final ASIC, the IgnitER (320x256 pixel matrix, 45 µm pitch, die size 1.6x1.4 cm2), now close to submission.
The Ignite64 implements and tests solutions for accurate power and clock distribution, which are key to obtain high and uniform performance in timing. Also, different solutions for the Analog Front End have been designed and tested, to accurately characterize their response concerning performance vs power and vs TID.
At 1 fC input charge and 10 µW per pixel, typical measured time resolution is around 20 ps (AFE + TDC) at 0 input capacitance, while it is still around 35 ps RMS when a 3D silicon sensor matrix is bonded on top of it (100 fF typical pixel capacitance). Value dispersion at the level of the full matrix is kept under control, with an RMS error around 5 ps on the distribution of resolutions per pixel. This demonstrates the success of the adopted architecture and circuital solutions for powering (localized LDO).
These and other results from the Ignite64 tests are a precious guide for the design of the IgnitER. In the present paper we describe and justify the architectural choices adopted for the IgnitER, as an output from the Ignite64 tests. Expected performance of the large-area ASIC, as obtained from IgnitER post-layout simulations, are also illustrated.