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Description
Next-generation pixel detectors for high-energy physics rely on high-speed links exceeding 10 Gbps, making efficient and reliable production quality control (QC) a critical challenge. This work introduces a high-speed wafer-level testing approach based on vertical probe card technology, enabling multi-Gbps validation directly at wafer-level. Test results obtained on MOSAIX, a MAPS developed for ALICE ITS3 experiment at CERN LHC and adopted by the ePIC SVT experiment at BNL EIC, demonstrate non-destructive, full functional chip characterization directly on a wafer prober, including data readout through high-speed links at 5.12 and 10.24 Gbps, while enabling parallel, high-throughput QC for next-generation detector production.
Summary (500 words)
Next-generation pixel detectors for high-energy physics experiments are expected to operate at increasingly high data rates, exceeding 10 Gbps. The MOnolithic Stitched Active pIXel (MOSAIX), a Monolithic Active Pixel Sensor (MAPS) developed for the Inner Tracking System (ITS)3 at the ALICE experiment at CERN Large Hadron Collider (LHC) and adopted by the Silicon Vertex Tracker (SVT) at the ePIC experiment at Brookhaven National Laboratory (BNL), integrates on-chip high-speed serializers operating at 5.12 and 10.24 Gbps.
For large-scale systems such as the ePIC SVT requiring the equivalent of 400 wafers of a MOSAIX-derived sensor, so-called Large Area Sensor (LAS), the integration of faulty devices into detector assemblies results in substantial costs, making comprehensive production quality control (QC) at wafer-level essential. However, wafer-level testing in high-energy physics traditionally relies on cantilever probe cards, typically limited to a few hundred MHz due to the high parasitic inductance (exceeding 10 nH) of the long probes used (>5 mm), preventing validation of high-speed links during QC and significantly increasing overall testing time.
Previous work established vertical probe card technology as a key enabler for wafer-level testing at multi-Gbps, using shorter probes (~1 mm) exhibiting lower inductance (~ 2 nH), ensuring an operating bandwidth exceeding 40 GHz. Building on this approach, the present work reports on MOSAIX characterization using a dedicated vertical probe card optimized for high-speed operation.
The developed setup combines a vertical probe card with a high-speed interconnect chain, ensuring reliable transmission of multi-Gbps data streams to the readout FPGA. The system is inherently modular, enabling multi-point probing, allowing simultaneous testing of up to three MOSAIX or LAS devices, significantly reducing full-wafer QC time.
Using this setup, comprehensive functional characterization of MOSAIX has been achieved, including eye diagram measurements at 5.12 and 10.24 Gbps and pixel data readout through the high-speed links. This enables, for the first time, non-destructive, wafer-level verification of complete MAPS functionality at Gbps rates. In contrast to conventional full verification based on carrier boards requiring wire bonding and gluing of the sensor to a PCB, the proposed method preserves device integrity while providing equivalent test coverage.
This work demonstrates the feasibility and advantages of high-speed wafer-level testing for next-generation pixel detectors. Based on MOSAIX characterization results, production QC throughput for the ePIC SVT is evaluated, showing how testing at full data rate significantly reduces overall testing time and ensures comprehensive functional validation of the sensors. Furthermore, the modular architecture enables parallel testing of multiple devices, providing an additional lever to scale throughput for large-volume production. For the ePIC SVT, for example, on-wafer production QC based on cantilever probe cards would require more than 7 years when operating three sites in parallel full time and would not allow to validate the 10 Gbps serializers; by contrast, combining vertical probing with parallel testing, a single site could complete the full production QC in less than 1 year. These results highlight high-speed, parallel wafer-level QC as a key requirement to meet the scale, speed, and performance demands of future detector systems.