Jun 13 – 15, 2012
LAL Orsay
Europe/Paris timezone

The development of the multi PPD readout electronics with EASIROC and SiTCP

Jun 15, 2012, 11:50 AM
20m
Amphithéâtre Pierre Lehmann (LAL Orsay)

Amphithéâtre Pierre Lehmann

LAL Orsay

Centre Scientifique d'Orsay - Bat 200 91898 Orsay cedex FRANCE
Oral presentation Electronics

Speaker

Ryotaro Honda (Tohoku University)

Description

We are developing an electronics to readout many PPDs for J-PARC (Japan Proton Acclerator Research Complex) E40 in Japan. In the E40 experiment, differential cross section of hyperon-proton scattering will be measured by using a liquid hydrogen target and high intensity pion beam (up to 10 MHz) in the K1.8 beamline. Two different types of new detectors, consisted of scintillation fibers and PPDs, are under development. One is a beamline fiber detector to measure the pion beam position and time of flight (TOF). The other is a cylindrical fiber tracker surrounding the target to measure the energy and scattering angle of the scattered protons. The total number of PPDs for these detectors will be about 5,000 channels. To handle such a large number of PPDs in our experiment, development of a serial readout electronics for PPDs is indispensable. All essential functions such as gain adjustment of PPD to data transmit to DAQ system should be included in one electronics to save cost. In addition, both of charge and timing measurements are required for our readout system. We are developing a new readout system for multi PPDs with Omega IN2P3 and KEK. The readout electronics consists of Extended Analogue SiPM Integrated Read Out Chip (EASIROC) developed by Omega in LAL in France and Silicon TCP (SiTCP) developed by KEK. EASIROC is an ASIC which can operate 32 channels of PPDs. EASIROC has the implemented features such as gain adjustment, double gain amplifier, discriminator, multiplexed analogue output and parallel discriminator outputs. By using SiTCP, we can use TCP/Ethernet data transmission without any expensive CPU. Charge and timing are measured by the pipeline ADC and digital Multi-hit TDC (MHTDC) in FPGA, respectively. The first version of the readout board has been developed. We evaluated performance for the charge and timing measurements and the data transmit speed. The mean DAQ rate is over 10 kHz. Implementation of MHTDC which has 2 us time window, 8 depth and 1 ns LSB resolution was succeeded. These performances are sufficient for J-PARC E40. In this conference, I'll introduce about the evaluation board and the test results.

Primary author

Ryotaro Honda (Tohoku University)

Co-authors

Christophe DE LA TAILLE (Omega IN2P3) Isamu Nakamura (Department of Physics) Koji Miwa (Tohoku University) Koji YOSHIMURA (High Energy Accelerator Research Organization (KEK)) Ludovic Raux (Omega IN2P3) Manobu Tanaka (Open-It) Masahiro Ikeno (Open-It) Stéphane Callier (Omega IN2P3) Tomohisa Uchida (Open-It)

Presentation materials