BGI Regular Meeting

Europe/Zurich
864/2-B14 - SALLE J.B.ADAMS (CERN)

864/2-B14 - SALLE J.B.ADAMS

CERN

25
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63808180348
Host
James Storey
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Present: Gunn, Hampus, James, Justus, Juri (Zoom), Lukas, Mark, William, Wilfried

1. HL-LHC BGI

1.1 CST + Virtual-IPM Simulations

Gunn presented updated CST + Virtual-IPM simulations based on Lauren’s latest 3D mechanical model. In the nominal configuration (uniform By = 0.6 T, E-field from CST, no mechanical misalignment), the relative sigma error remains below 2%, confirming acceptable profile distortion in the ideal case.

Systematic angular misalignments were introduced around the X, Y and Z axes. Rotation around the X-axis (pitch) was identified as the dominant sensitivity, producing E×B drift and visible profile distortion as the tilt approaches ~1°. Rotations around Y and Z have significantly smaller impact. A 200 µm mechanical offset corresponds to ~0.05° tilt, which lies comfortably within the acceptable regime.

Conclusion: Current mechanical alignment tolerances (O(100 µm)) appear sufficient for HL-LHC requirements. A formal tolerance value will be defined.


1.2 Magnet & Mechanical Integration

Dominique requested confirmation of the transverse space envelope before freezing the magnet design. Available margins for the PCB, HV routing and associated components were reviewed. No immediate blocking conflicts were identified, although only a few millimetres of margin remain in some areas.

Particular attention is required for:

  • Minimum bending radius of the 40 kV cable.

  • Space allocation for impedance matching components.

A final confirmation will follow review of Lauren’s updated layout.


1.3 HV Feedthrough & Impedance Matching

Approximately 70 W of RF-related power may need to be handled in the impedance matching region near the HV feedthrough. Several integration strategies were discussed, including locating the matching network near the feedthrough or remotely in a floor-mounted enclosure.

The impedance matching concept must be defined before feedthrough procurement. Preliminary considerations suggest that small impedance mismatches are tolerable, but a formal solution is required prior to design freeze.


1.4 Ceramic–ASIC–CuW Assembly

Progress continues on the ceramic–CuW–Timepix4 stack attachment strategy. Brazing of ceramic to CuW is considered feasible, provided compatible material selection and controlled thermal sequencing are applied. Flip-chip bonding remains compatible with the proposed stack.

Vacuum compatibility and outgassing tests will be performed before final material selection. Brazing and adhesive approaches remain under parallel evaluation.


2. PS & SPS BGI

2.1 DAQ – Timepix4 v5 Status

The Timepix4 v5 DAQ implementation is progressing and remains within overall schedule margin, despite a short internal delay related to state-handling and integration issues.

The following functionality is implemented:

  • Pixel configuration (read/write)

  • Mask handling

  • Register access

  • Event acquisition

  • File storage

  • Backend deployment at PS and SPS

The focus now shifts to systematic hardware validation and debugging.


2.2 Real-Time Data Processing & Profile Publication

The architecture writes raw detector data to disk while a consumer process reads the file in memory to reconstruct profiles in real time. FESA publishes the results at the end of each machine cycle.

Full end-to-end validation (detector → file → profile reconstruction → FESA publication) remains to be completed under realistic operating conditions.


2.3 Equalisation & Software Architecture

The equalisation procedure is implemented in the core library layer, wrapping the low-level hardware extender. FESA calls high-level functions only, maintaining separation between hardware access and operational control.

Source-based calibration remains an offline procedure. The Expert GUI is not currently a blocking item.


3. Actions

HL-LHC BGI

  • Provide formal angular tolerance recommendation (max acceptable θx tilt).
    Responsible: Gunn

  • Confirm minimum bending radius of 40 kV cable and check layout compatibility.
    Responsible: Gunn

  • Review transverse space envelope and confirm to TE-MSC.
    Responsible: Lauren

  • Define impedance matching strategy in consultation with ABT.
    Responsible: Mark


PS & SPS BGI

  • Complete hardware validation of Timepix4 v5 DAQ chain.
    Responsible: DAQ team

  • Validate full real-time processing chain and FESA publication.
    Responsible: DAQ team

  • Test equalisation procedure with hardware integration.
    Responsible: DAQ team

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