31 August 2026 to 4 September 2026
US/Pacific timezone

Tutorial on HGQ, Alkaid, and Top-Level-Synthesis for End-to-end system design

31 Aug 2026, 11:00
1h 30m
QI Theater

QI Theater

Tutorial Tutorials

Speaker

Chang Sun (California Institute of Technology (US))

Description

Real-time inference with sub-microsecond latency is critical for the Level-1 trigger systems at the High-Luminosity LHC. We present an end-to-end, open-source framework that spans model optimization, quantization, and FPGA deployment, enabling the translation of high-level neural network or generic dataflow models into resource-efficient FPGA implementations.

We intro HGQ and Alkaid, the SOTA frameworks for low-latency FPGA-aware quantization aware training and mapping neural networks onto FPGAs. HGQ optimizes the neural networks, either classical or LUT-based, with differentiable bitwidths and hardware aware losses. On the backend, Alkaid converts the trained model, along with potentially required pre-/post-processing operations, such as clamp, sorting, or histograming, into optimized and synthizable RTL, HLS, or XLS IR. Advanced optimizations, such as distributed arithmetic, affine arithmetic, and ternary adder fusions, are applied. Accurate, white-box performance model is also provided for resource utilization and latency of the firmware. Compared to hls4ml, Alkaid achieves more than half LUT reduction compared to hls4ml and 20-20% compared to hls4ml+da4ml for a 1:1 bit-exact model implementation.

This tutorial will cover the following:

- Frequent tunable knobs of HGQ
  - quantizer config
  - beta scheduler/controller
- Basics of LUT-based layers
- Defining and training small Jet tagger with MLP and LUT-MLP
- Defining and training JEDI-Linear
- Converting MLP and LUT-MLP with Alkaid
  - Resource and latency surrogate
  - disable certain optimization and compare results
- Bit-exact emulation and model save/load
- Implementing finite state machine
  - Converting JEDI-Linear with Alkaid
    - Kernel-level resource reuse (i.e., parallelization factor)
    - Prepend a sorting network to the NN
  - Defining systolic arrays and FIFOs
  - Implement a toy MLP in "resource mode"
- Frontend parser plugin interface (framework- and op-level)
- Top-Level-Synthesis: LLM-native solution for end-to-end system design
  - Demo: Jet tagging benchmark
  - Demo:realtime application
Tutorial level (only for Tutorial) Intermediate

Author

Chang Sun (California Institute of Technology (US))

Co-authors

Maria Spiropulu (California Institute of Technology (US)) Wayne Luk Zhiqiang Que (University of Bristol)

Presentation materials