31 August 2026 to 4 September 2026
US/Pacific timezone
All in-person registration fee waivers have now been claimed.

Session

Tutorials

31 Aug 2026, 09:00

Presentation materials

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  1. Dr Javier Hernandez Nicolau (San Diego Supercomputer Center, UC San Diego), Dr Madhusudan Gujral (San Diego Supercomputer Center, UC San Diego), Dr Mahidhar Tatineni (San Diego Supercomputer Center, UC San Diego)
    Tutorial

    This tutorial will present the architecture, Kubernetes based systems setup, user software environment, scalability studies, and fine tuning on the Voyager system. Voyager is an US National Science Foundation funded AI-focused hardware based supercomputer. It is built using the Intel/Habana Gaudi processors (Gaudi1 and Gaudi2), has a 400 GbE interconnect from Arista for scale out training and...

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  2. Georgios Flengas (CERN), Marius Köppel (ETH Zurich (CH))
    Tutorial

    For the deployment of machine learning (ML) models with strict requirements on latency and computing resources, field-programmable gate arrays (FPGAs) have emerged as a preferred hardware platform, as they offer low-level hardware control and easy reprogrammability. However, deploying models on these devices requires expert knowledge of dedicated programming techniques, such as high-level...

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  3. Romina Soledad Molina
    Tutorial

    Abstract
    Deploying neural networks on FPGAs remains a significant barrier in embedded AI. Exploring the design space across compression strategies (pruning, quantization, knowledge distillation) and hardware configurations is often fragmented, requiring deep expertise across multiple toolchains.

    This tutorial introduces KalEdge, a hardware-aware platform unifying the ML-to-FPGA...

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  4. Chang Sun (California Institute of Technology (US))
    Tutorial

    Real-time inference with sub-microsecond latency is critical for the Level-1 trigger systems at the High-Luminosity LHC. We present an end-to-end, open-source framework that spans model optimization, quantization, and FPGA deployment, enabling the translation of high-level neural network or generic dataflow models into resource-efficient FPGA implementations.

    We intro HGQ and Alkaid, the...

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