Advanced Compute Scaling in the Angstrom Era of Integrated Circuit Technologies

by Anabela Veloso (Imec)

Friday 8 May 2026, 11:00 → 12:00 Europe/Zurich

40/S2-C01 - Salle Marie Sklodowska-Curie (CERN)

The need for increased computing keeps growing at ultra high speed, required to support an ever larger and wider range of applications, with generative artificial intelligence (AI) significantly accelerating this trend. Additionally, as the projected AI power consumption growth is unsustainable, energy efficiency is increasingly becoming the most important performance index. Innovations in various domains of integrated circuit technologies are crucial for enabling this, required to continuously increase the transistor density and obtain enhanced chip performance and efficiency levels. Logic standard cell shrinkage remains therefore at the core of the compute roadmap. Its momentum is expected to carry on, even as 2D scaling has become increasingly challenging, by introducing novel device architectures, new materials, scaling boosters like backside (BS) power delivery (BSPD), and an overall increased use of design-technology co-optimization (DTCO)-driven design improvements.

A key support pillar of the roadmap remains continued dimensional scaling, enabled by progressive advances in holistic patterning which increasingly rely on the use of extreme ultraviolet (EUV) lithography (evolving into high numerical aperture (NA) EUV lithography) to obtain cost-effective scaling and considerably lower energy consumption. At transistor level, nanosheet (NS)-based FETs are taking the central stage, first as single-level devices consisting of several vertically stacked NS per device, and potentially evolving into 3D stacked configurations like the so-called complementary FET (CFET) where opposite polarity NSFETs are folded on top of each other and different materials/crystal orientations can be potentially used for the stacked channels.

Exploring further the third (vertical) dimension is, in fact, a common current trend of both logic and memory roadmaps, with new options for achieving more energy-efficient systems thanks to recent advances in bonding, backside, 3D and photonic technologies allowing unprecedented interlayer connectivity besides the typical on-chip interconnects at system-on-chip (SoC) level and functional specialization per tier. In parallel, despite the performance and energy-efficiency gains, the compute density increase is making thermal management and heat dissipation solutions ever more critical.

This presentation aims to highlight and discuss some of these key advances, including challenges and opportunities, occurring in the area of advanced compute/logic scaling, wherein exciting, sustainability-aware innovations with increased interdisciplinary synergies are shaping the roadmap ahead.

 

 

Coffee will be served at 10:30