CERN openlab-Intel MIC / Xeon Phi training

Name: CERN openlab-Intel MIC / Xeon Phi training
Start: 2013-04-11T09:00:00+02:00
End: 2013-04-12T17:00:00+02:00
Location: CERN

11 Apr 2013, 09:00 → 12 Apr 2013, 17:00 Europe/Zurich

TBC (CERN)

TBC

CERN

Description

Update: Registrations are closed, the course is full

We are planning a dedicated, hands-on Intel MIC / Xeon Phi course at CERN, organized by openlab and delivered by two experts from Intel on April 11^th-12^th. The session will be at an introductory/intermediate level, and it will be an excellent opportunity to ask the knowledgeable tutors questions. The tentative agenda, which will be adjusted based on your comments, is as follows:

Hardware and software overview
Programming models, including threading, vectorization, offloading, MPI
Performance analysis with VTune and Intel Trace Analyzer/Collector
Hands-on labs including offload memory and MPI exercises

We would appreciate it if you could register in case you are interested, and let us know by e-mail what you would like to learn and if you would like to attend the hands-on in addition to the lectures. The program can and will be adapted to suit your needs as far as possible. Any questions or technical issues signaled to the trainers in advance have a higher chance of being addressed in detail.

We look forward to your feedback.

The agenda of this meeting is empty