Speaker
Mr
Rose Andrew William
(Imperial College - University of London)
Description
The LHC has been described as a statistics machine, using very high interaction rates to compensate for the very low cross-sections of ‘new’ (interesting) physical processes. Were the detector to be read out continually a data rate of around 5x10^7 Mbyte/s (~50Tbyte/s) would be routine, the vast majority of which is of no interest. To reduce this to a storable (100MByte/s) rate, two levels of triggering are used; the Level-1 trigger (custom hardware) and the Higher-Level Trigger (software).
I discuss here the current level-1 trigger architecture, the complications introduced by the increased luminosity of the proposed accelerator upgrade (SLHC) and several solutions currently under investigation.
| Talk, Poster, or Talk & Poster | Talk |
|---|
Author
Mr
Rose Andrew William
(Imperial College - University of London)