Speaker
Dr
Sami Kama
(Southern Methodist University (US))
Description
The challenge faced by HEP experiments from the current and expected architectural evolution of CPUs and co-processors is how to successfully exploit concurrency and keep memory consumption within reasonable limits. This is a major change from frameworks which were designed for serial event processing on single core processors in the 2000s. ATLAS has recently considered this problem in some detail through its Future Frameworks Requirements group.
Here we report on the major considerations of the group, which was charged with considering the best strategies to exploit current and anticipated CPU technologies. The group has re-examined the basic architecture of event processing and considered how the building blocks of a framework (algorithms, services, tools and incidents) should evolve. The group has also had to take special care to ensure that the use cases of the ATLAS high level trigger are encompassed, which differ in important ways from offline event processing (for example, 99% of events are rejected, which must be done with minimum resource investment). Finally, the group has considered how best to
use the wide variety of concurrency techniques, such as multi-processing, multi-threading, offloaded accelerator technology, parallel I/O, and how to exploit resources such as high performance computing sites.
Primary author
Graeme Stewart
(University of Glasgow (GB))
Co-authors
Benjamin Michael Wynne
(University of Edinburgh (GB))
Charles Leggett
(Lawrence Berkeley National Lab. (US))
Dr
David Malon
(Argonne National Laboratory (US))
John Baines
(STFC - Rutherford Appleton Lab. (GB))
Paolo Calafiura
(Lawrence Berkeley National Lab. (US))
Dr
Sami Kama
(Southern Methodist University (US))
Tomasz Bold
(AGH Univ. of Science and Technology, Krakow)
Walter Lampl
(University of Arizona (US))
