A multi-port 10GbE PCIe NIC featuring UDP offload and GPUDirect capabilities.

Not scheduled
15m
OIST

OIST

1919-1 Tancha, Onna-son, Kunigami-gun Okinawa, Japan 904-0495
poster presentation Track8: Performance increase and optimization exploiting hardware features

Speaker

Andrea Biagioni (INFN)

Description

NaNet-10 is a four-ports 10GbE PCIe Network Interface Card designed for low-latency real-time operations with GPU systems. For this purpose the design includes a UDP offload module, for a fast and deterministic to clock-cyle handling of transport layer protocol, plus a GPUDirect P2P/RDMA engine for low-latency communication with nVIDIA Tesla GPU devices. A dedicate module (Merger) can optionally process input UDP streams before data are delivered through PCIe DMA to their destination devices, e.g. coalescing payload data from different streams according to a reconfigurable algorithm. NaNet-10 is going to be integrated in the NA62 CERN experiment in order to assess the suitability of GPGPU systems as real-time triggers, we will report results and lessons learned in this activity.

Primary authors

Alessandro Lonardo (Universita e INFN, Roma I (IT)) Andrea Biagioni (INFN) Davide Rossetti (nVIDIA Corp.) Dr Elena Pastorelli (INFN - Sezione di Roma) Dr Francesca Lo Cicero (INFN - Sezione di Roma) Francesco Simula (INFN - Sezione di Roma) Laura Tosoratto (INFN) Dr Michele Martinelli (INFN - Sezione di Roma) Dr Ottorino Frezza (INFN - Sezione di Roma) Dr Pier Stanislao Paolucci (INFN - Sezione di Roma) Piero Vicini (INFN Rome Section) Roberto Ammendola (INFN)

Co-authors

Gianluca Lamanna (INFN LNF) Dr Luca Pontisso (INFN - Sezione di Pisa) Marco Sozzi (Sezione di Pisa (IT))

Presentation Materials