11–13 Feb 2015
Other Institutes
Africa/Johannesburg timezone

Development and Testing of a High Data Throughput ADC Board for the Prometeo Portable Test-bench System for the Certification of the ATLAS Tile Hadronic Calorimeter

13 Feb 2015, 09:20
20m
iThemba LABS - Gauteng (Other Institutes)

iThemba LABS - Gauteng

Other Institutes

Cnr Jan Smuts Ave & Empire Road, Braamfontein Private Bag11, WITS 2050, South Africa

Speaker

Matthew Spoor (University of the Witwatersrand (ZA))

Description

M. Spoor The LHC has been undergoing its first long shut down (LS1) in preparation for the Phase–II upgrade scheduled for 2024. Once upgraded the LHC will begin its high Luminosity Phase, increasing the beam luminosity by a factor of 5 to 7. The upgrade requires a redesign of the electronics systems of the ATLAS tile hadronic calorimeter (TileCal) and thus a hybrid demonstrator system is in development to act as a validation of the new read-out architecture. A new stand-alone test-bench system used for the certification of the ATLAS TileCal is also in the process of being developed for the Phase-II upgrade of LHC in 2024. The Prometeo (A Portable ReadOut ModulE for Tilecal ElectrOnics) test-bench is planned to replace the current generation Mobidick 4 system, improving portability, expanding its functions as well as being compatible with the new TileCal Hybrid demonstrator. The design provides all the functionalities needed to assess the certification procedure of a single mini-draw of the TileCal. At the centre of each Prometeo system lies a Xilinx Virtex-7 FPGA which can be accessed through Ethernet via IPbus. Fibre optic connections provide communication with the front end electronics. A HV board delivers high voltage signals to turn on the gain of the PMTs, while a LED driver is used to provide fast pulses to trigger the PMTs. A new ADC board is currently being developed and tested for the Prometeo system. The prototype was based on the original Mobidick system which used two 8 channel 12-bit ADCs to sample differential analog signals coming from the trigger towers. The sampled data is serialised and sent to the FPGA via an FMC expansion port at a data rate of 640 Mbps. The ADC board including the firmware was designed and assembled by the University of Witwatersrand. The design is currently in its testing phase and next generation prototype is will be sent for fabrication at the end of February 2015.

Presentation materials