Speaker
Description
Summary
The high demands in terms of computational power and data latency posed on the
electronics of the LHC experiments require in many cases the development of
specialized hardware. As available standard systems and network components are not
directed towards the requirements of high energy physics, they do for example
introduce a data delay that is not acceptable for low-latency trigger systems.
The module presented here is being developed for the transition radiation detector
(TRD) of ALICE. It is an FPGA-based system utilizing PCI and 12 fibre-optical
transceiver interfaces, realized as a CompactPCI plug-in card.
The experimental requirement driving the development of the presented module is the
ALICE TRD trigger. Local online tracking data is shipped off of the detector
modules situated in 6 layers via 1080 fibre-optical links. The trigger decision
requires tracking over the 6 TRD layers and full event reconstruction in less than 2
microseconds. This demands for high-speed computation and low-latency transmission
along the complete data path. To perform the FPGA-based tracking algorithm for
different regions of the detector, 90 of the presented modules will be used.
The Compact-PCI (cPCI) specification describes an interface that is basically an
adoption of the PCI specification to the 3U/6U sub-rack module form-factor. This
form-factor is widely used in industrial and also high-energy physics applications.
By implementing a 64 Bit wide 33 MHz cPCI interface, the presented module easily
interfaces to COTS components like cPCI CPU boards and power supplies. This
interface can be used not only for system management and testing, but also for
medium-bandwidth data transmission in experimental test setups.
For high-speed data reception, the module features 12 separate serial interfaces
implemented as SFP (small form-factor pluggable)sockets on the front panel. By
utilizing the SFP form-factor, a wide range of commercially available SFP fibre-
optical transceivers can be used. In the present version of the board, a data rate
of up to 2.4 GBit/s per link is supported. The resulting total incoming data rate
is 2.9 GByte/s. Three independent 8-Bit wide source synchronous LVDS interfaces
allow for low-latency connection to other modules via backplane.
The main FPGA used on the board is a Xilinx Virtex-4 FX chip. This series of FPGAs
provides not only up-to-date performance but also integrated multi-gigabit
serializer/deserializer (serdes) blocks and PowerPC processor blocks. The
integrated serdes blocks provide a fast and flexible interface of the serial inputs
to the FPGA fabric. A second FPGA is used for system management and control tasks.
Three identical 36-Bit wide QDR2-SRAM chips provide a high-bandwidth memory
of 55.3 MBit size which can be used for event buffering. Running at 120 MHz DDR,
the total memory bandwidth is 51.8 GBit/s. This is enough to sink the incoming peak
data rate.
