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11th Workshop on Electronics for LHC and future Experiments

→ Europe/Zurich
Heidelberg

Heidelberg

Germany
Description
The workshop will cover all aspects of electronics for high rate particle colliders, underground and neutrino experiments, astrophysics and space applications. Emphasis will be placed on R&D for future experimentation including developments in deep sub-micron technologies. Please note that the Wednesday session will be a more interactive workshop session with both talks and discussion interspersed, so the agenda should be treated as a guide.
Support
  • Monday 12 September
    • Plenary session P1
      • 1
        Introduction
        Speaker: Local organisers
      • 2
        Commissioning the LHC machine
        After a brief reminder of the installation schedule and the performance goals that the LHC aims to achieve, the strategy for commissioning with protons is presented. Dedicated runs with ions and protons are mentioned, and how machine operation may be scheduled through a year is shown. Potential trouble spots during the operational cycle are then highlighted and an estimate of the resultant particle losses given.
        Speaker: Dr Roger Bailey (CERN)
        Paper
        Slides
      • 3
        The LHC Machine interface; Status - Challenges - Outlook
        The impact of particle losses on the operation of the LHC machine and experiments will be discussed. It will be shown how the risk of radiation induced failure to equipment can be reduced via shielding, radiation tolerant equipment designs and on- line radiation monitoring. A number of critical cases for the LHC Machine Experiments interface will be highlighted. Recent data on beam induced backgrounds and radiation at CDF (Fermilab) will be shown.
        Speaker: Dr Thijs Wijnands (CERN)
        Slides
      • 15:45
        break
      • 4
        Distributed power in space systems
        Distributed power systems offer many benefits to system designers over central power systems such as reduced weight and size. Distributed systems also allow the designers to control the quality of power at different loads and subsystems, since DC-DC converters allow close regulation of output voltage under wide variations of input voltages and loads. Distributed power systems also provide a high degree of reliability because of the isolation provided by DC/DC converters; it is very easy to isolate system failures and provide redundancy. These systems are also very flexible and easily expanded. This talk will address the DC distributed power system of the International Space Station, which is a specific case of this kind of distributed system. It is a channelized, load following, DC network of solar arrays, batteries, power converters, switches and cables which route current to all user loads on the station. The completed architecture consists of both the 120-V American and 28-V Russian electrical networks, which are capable of exchanging power through dedicated isolating converters. The presence of DC/DC converters required special attention on the electrical stability of the system and in particular, the individual loads in the system. This was complicated by complex sources and undefined loads with interfaces to both sources and loads being designed in different countries (US, Russia, Japan, Canada, Europe, etc.). These issues, coupled with the program goal of limiting costs, have proven to be a significant challenge to the program. As a result, the program used an impedance specification approach for system stability. This approach is based on the significant relationship between source and load impedances and the effect of this relationship on system stability. It is limited in its applicability by the theoretical and practical limits on component designs as presented by each system segment. Consequently, the overall approach to system stability implemented by the ISS program consists of specific hardware requirements coupled with extensive system analysis and hardware testing. Highlights of both experimental and analytical activities will be shown, as well as some lesson learned during the development and operational phase of Modules and payloads.
        Speaker: Prof. Antonio Ciccolella (ESA-ESTEC)
        Slides
      • 5
        Design and Performance of the IceCube Electronics
        The first sensors of the IceCube Neutrino Observatory were deployed at the South Pole in January 2005 – 60 modules on one string at depths from 1450 to 2450 meters and 16 modules in eight tanks at the surface. We present an overview of the electronics for IceCube and demonstrate their performance with experimental data obtained for cosmic ray muons. Analog waveforms of pmt signals are digitized and time stamped in themodules. Photon arrival times are determined to a precision of 4 nanoseconds for modules connected to the surface by twisted-pair copper wires nearly 3 km long.
        Speaker: Dr Robert Stokstad (Lawrence Berkeley National Laboratory, for the IceCube Collaboration)
        Paper
        Slides
    • 19:00
      Reception : Light refreshment and snacks
  • Tuesday 13 September
    • Plenary Session P2
      • 6
        CMOS Technology Characterization for analog/RF application
        We discuss state of the art and new developments for the characterization of CMOS technologies. In the first chapter the most important issues of MOS transistor modeling will be shown. Topics like AC/DC modeling, noise modeling and temperature modeling for the MOS transistor will be explained. State of the art MOS transistor models like the BSIM3 and BSIM4 models as well as the newest surface potential and charge based models will be highlighted. This article touch on a few of the issues that are important for RF design. However the bottom line is the existence of high accurate S-Parameter measurements and frequency dependent SPICE models not only for the active devices like MOS transistor and varractors, also for passive devices like resistors, inductors and capacitors. CMOS technologies include also additional parasitic devices like PNP bipolar transistors, which should be modeled very carefully for different analog applications like band-gap reverence circuits. And last but not least the very important topic statistical modeling including worst case corner modeling, Monte Carlo simulation, statistical boundary modeling and mismatch parameter will be discussed.
        Speaker: Dr Ehrenfried Seebacher (Austriamicrosystems)
      • 7
        0.13 um CMOS technologies for analog front-end circuits in LHC detector upgrades
        Deep submicron CMOS technologies are widely used for the implementation of low noise front-end electronics in various detector applications. In this field the designers’ effort is presently focused on 0.13 micron technologies. This work presents the results of noise measurements carried out on CMOS devices in 0.13 um commercial processes from different foundries. The study also includes an evaluation of the impact of high doses of ionizing radiation on the noise performances. Data obtained from the measurements provide a powerful tool to model noise parameters and establish design criteria in a 0.13 um CMOS process for detector front-ends in LHC upgrades.
        Speaker: Dr Massimo Manghisoni (Università degli Studi di Bergamo)
        Paper
        Slides
      • 8
        Operational Experience with the CDF Run II Silicon detector
        The CDF Silicon Vertex detector consists of three subdetectors: SVX-II, ISL and L00. Altogether it consists of 8 layers of Silicon with more than 750000 readout channels. This detector is essential for CDF's high precision tracking and is vital for the forward tracking capabilities and the identification of heavy flavor decays. After four years of data taking in Run-II and a delivered luminosity of almost 1 fb-1 a summary of the operational experiences with a silicon detector at CDF is given. Besides being very important for the tracking, the Silicon detector also plays a vital role in Level 2 decision of the CDF Trigger system. Results from off-line reconstruction showing the detector resolution and tracking efficiency are presented as well. Finally aspects of the longevity of this Detector and the impact on the CDF physics program are presented.
        Speaker: Dr Marcel Stanitzki (Yale University)
        Paper
        Slides
    • 10:35
      break
    • Parallel session A1
      • 9
        A VLSI Full Custom ASIC Front End for the Optical Module of NEMO Underwater Neutrino Detector
        A cubic KM scale underwater neutrino detector requires thousands of photomultipliers whose signal must be acquired and transferred through an electro-optical cable to shore for analysis and storage. The transferrable power and data bandwidth of this cable is limited. The work described here has been developed in the context of the NEMO Collaboration with the aim of studying and designing a front-end electronics for the Optical Modules, which contain the telescope optical sensors, as a full-custom Very Large Scale Integration (VLSI) Application Specific Integrated Circuit (ASIC). The advantages of this solution are manifold. The most important are low power consumption and the pre-analysis and opportune reduction of data to be transferred to the shore station for acquisition. A detailed description of the chosen architecture and the design principles of the blocks, that carry out the specialized function required by this architecture, will be given. The chips produced will be described and the test measurements performed will be shown.
        Speaker: Dr Domenico Lo Presti (Catania University-Physics Department)
        Paper
        Slides
      • 10
        Delay25, an ASIC for timing adjustment in LHC
        A five channel programmable delay line ASIC was designed, fabricated and tested. The IC features 4 channels that allow to phase delay periodic or non-periodic digital signals and a master channel that can be used to phase delay a clock signal. The master channel serves as a calibration reference guaranteeing independence from process, supply voltage and temperature variations. The phase of each channel can be independently programmed with a resolution of 0.5 ns through an I2C interface. The reference clock frequency can be 32, 40, 64 or 80 MHz. The ASIC is manufactured in a 0.25 m CMOS standard technology using radiation tolerant layout practices. The measured output jitter for the master channel is below 10 ps (rms) and below 20 ps (rms) for the replica channels.
        Speaker: Mr Hugo Furtado (CERN)
        Paper
        Slides
      • 11
        The 0.25um Token Bit Manager for CMS Pixel Readout
        To coordinate groupings of pixel readout chips, the Token Bit Manager (TBM), has been developed for the CMS experiment. The TBM will coordinate passing of the readout token around a group readout chips (ROC). In addition it supplies the DAQ with a header and trailer record to facilitate event recognition. Also present on the same chip is a Control Network Hub, which directs control commands to the TBM, as well as the ROC. The Latest design details, and resent performance measurements will be presented, including the results of radiation and low temperature testing.
        Speaker: Mr Edward Bartz (Rutgers University)
        Paper
        Slides
      • 12
        A current-based readout ASIC with on chip pedestal subtraction and zero suppression for a fast readout at a future collider
        For a very fast readout of a DEPFET pixel matrix at the ILC (International Linear Collider) the 128 channel CURO II ASIC has been designed and fabricated in a 0.25 µm process. Due to the signal of the sensor being a current, the architecture of the chip is completely based on current mode (SI) techniques. This comprises double-correlated-sampling in the analog front end with current- memory-cells and a simultaneous current compare. Zero suppression of the data is done also on chip by a hit finder arranged in parallel. Measurements on the readout chip show a performance close to the ILC-requirements. A complete DEPFET pixel system has been operated using the CURO chip in detecting 6keV photons achieving a total system noise level of ENC < 250 e-.
        Speaker: Mr Marcel Trimpl (Bonn University)
        Paper
        Slides
    • Parallel session B1
      • 13
        The ATLAS Level-1 Central Trigger Processor
        The ATLAS Level-1 Central Trigger Processor (CTP) combines information from calorimeter and muon trigger processors and makes the final Level-1 Accept (L1A) decision on the basis of lists of selection criteria (trigger menus). In addition to the event-selection decision, the CTP also provides trigger summary information to the data acquisition system and the Level-2 trigger. It further provides accumulated and bunch-by-bunch scaler data for monitoring of the trigger, detector and beam conditions. The CTP will be presented and results will be shown from tests with the calorimeter and muon trigger processors connected to detectors in a particle beam, as well as from stand-alone full-system tests in the laboratory which were used to validate the CTP.
        Speaker: Mr Ralf Spiwoks (CERN)
        Paper
        Slides
      • 14
        Configuration of the ATLAS trigger
        The ATLAS detector at CERN's LHC will be exposed to proton-proton collisions at a rate of 40 MHz. In order to reduce the data rate, only potentially interesting events are selected by a three-level trigger system. Its first level is implemented in electronics and firmware, and aims at reducing the data output rate to about 75 kHz. The second and third trigger levels are based on software and reduces the rate to about 200 Hz. To prepare the full trigger chain for the online event selection according to a certain strategy, a system is being set up that provides the corresponding information to all parts of the trigger chain, e.g. values for hardware registers in level-1 or steering parameters of high-level trigger algorithms. The same information is used to configure the offline trigger simulation. In this presentation an overview of the system is given and its main components are discussed.
        Speakers: Joannes HALLER (CERN), Ralf Spiwoks (CERN)
        Paper
        Slides
      • 15
        ATLAS Level-1 Trigger Timing and Monitoring
        The ATLAS detector at CERN's LHC will be exposed to proton-proton collisions at a bunch-crossing rate of 40 MHz. In order to reduce the data rate, a three-level trigger system selects potentially interesting events. Its first level is implemented in electronics and firmware, and aims at reducing the output rate to under 100 kHz. The Central Trigger Processor (CTP) combines information from the calorimeter and muon trigger processors, and makes the final Level-1 Accept (L1A) decision. The CTP is a central element in the timing setup of the experiment. Several strategies are presented for timing-in the experiment, which is done with respect to the Level-1 trigger, with respect to the experiment, and with respect to the world. Furthermore, the monitoring of the Level-1 trigger is described. As trigger rates are very sensitive to beam conditions (luminosity, backgrounds) and detector performance (e.g. noisy cells), the Level-1 trigger needs to be carefully monitored, which guarantees correct functioning of the Level-1 trigger system and is vital for correct and meaningful data taking.
        Speaker: Mr Thilo Pauly (European Organization for Nuclear Research (CERN))
        Paper
        Slides
      • 16
        Implementation and Test of the First-Level Global Muon Trigger of the CMS Experiment
        In CMS, three independent first-level muon trigger systems identify muon candidate tracks. The Global Muon Trigger (GMT) receives up to 16 candidate tracks and combines them using algorithms exploiting the complementarity of the muon systems. The GMT also correlates the muon candidate tracks with calorimeter regions in order to determine muon isolation or confirmation by the calorimeter. The top four muon candidates are forwarded to the Global Trigger. The GMT algorithms are implemented in ten Xilinx Virtex-II FPGAs on a single 9U-VME board. The development of the VME board and its firmware as well as the results of system and integration tests are presented.
        Speaker: Mr Hannes Sakulin (Institute for High Energy Physics, Vienna, and CERN)
        Slides
      • 17
        THE ALICE CENTRAL TRIGGER PROCESSOR SYSTEM
        The Alice Central Trigger Processor is described. The current trigger concept was introduced in 2001 and allows up to 50 trigger inputs at three different levels: level 0 (24 inputs, 1.2 μs latency); level 1 (20 inputs, 6.5 μs latency); level 2 (6 inputs, 88 μs latency). Up to 50 trigger classes (where inputs and destination detectors are specified) can be used simultaneously. Detailed designs became available in 2005. The trigger system is implemented using seven types of 6U VME boards. Six types make up the CTP itself; the seventh, the LTU, provides the detector interface and can also be used as a trigger generator.
        Speaker: Dr Orlando Villalobos Baillie (University of Birmingham)
        Paper
        Slides
    • 13:05
      break
    • Parallel session A2
      • 18
        Evaluation of the Radiation Tolerence of SiGe Heterojunction Bipolar Transistors Under 24GeV Proton Exposure
        For the potential use in future high luminosity application in HEP (e.g. the LHC upgrade), we evaluated the radiation hardness of a candidate technology for the front-end of the readout ASIC for silicon strip detectors. The devices were test transistors of various geometries manufactured in the first generation, IBM SiGe 5HP process. Current gain as a function of collector current has been measured at several stages: before and after irradiation with 24 GeV protons up to fluences of 1016 p/cm2, and after annealing at elevated temperature. The analog section of an amplifier for silicon strips typically has a special front transistor, chosen carefully to minimize noise and usually requiring a larger current than the other transistors, and a large number of additional transistors used in shaping sections and for signal-level discrimination. We will discuss the behavior of both kinds of transistors, with a particular focus on issues of noise, power and radiation limitations.
        Speaker: Mr N. Spencer (UC Santa Cruz)
        Slides
      • 19
        Irradiation tests of the complete ALICE TPC Front-End Electronics chain
        The ALICE TPC Front End Electronics will be operated in a radiation field of up to 800 hadrons/cm2sec. SRAM-based FPGAs are used on the Front-End Cards (FEC) and the Read-out Control Units (RCU). Several irradiation tests of all components on the cards have ensured that the components selected are able to withstand the radiation environment, but have also shown that single event upsets will occur in the FPGAs. As system stability and endurance are major concerns, effort has been put into making the design radiation tolerant, for instance by using the active reconfiguration option as given by the Xilinx Virtex-II pro FPGA. The radiation tolerance of the final system will be verified by irradiation in a neutron beam at TSL
        Speaker: Mr Ketil Røed (Faculty of Engeneering, Bergen University College, Norway)
        Paper
        Slides
      • 20
        A radiation-tolerant LDO voltage regulator for HEP applications
        We have developed a radiation-tolerant Low Drop-Out (LDO) voltage regulator for applications in High Energy Physics experiments. The regulator outputs a fixed voltage of 2.5V, it provides a maximum current of 300mA with a drop-out as low as 150mV. The circuit incorporates over-current, over-voltage and over-temperature protection, and it can be disabled via a dedicated input pin. Manufactured in a commercial quarter-micron CMOS technology, it is available in a very compact 4.9x6x1.6mm 16L-EPP-SSOP package.
        Speaker: Dr Federico Faccio (CERN)
        Paper
        Slides
      • 21
        The TRAcklet Processor chip for the ALICE TRD
        The ALICE TRD has over 1,2 million analog channels that will be digitized at 10MSPS with 10-bit resolution. We have developed a TRAcklet Processor (TRAP) ASICs implementing 22 extra low power ADCs, digital filters, four RISC processors with shared memory, slow control serial interface and fast parallel 4-in 1-out readout tree ports. Together with the preamplifier chip they build a low-cost custom Ball Grid Array (BGA) Multi Chip Module (MCM), which is directly soldered on the readout board. Fully automated Wafer- and MCM- tester were developed. The TRAP design is finalized and the production is started.
        Speaker: Dr Venelin Angelov (KIP, Uni-Heidelberg)
        Slides
    • Parallel session B2
      • 22
        Radiation Tolerant Source Interface Unit for the ALICE Experiment
        The ALICE Detector Data Link (DDL) is a high-speed optical link designed to interface the readout electronics of ALICE sub-detectors to the DAQ computers. The Source Interface Unit (SIU) of the DDL will operate in radiation environment. Tests showed that configuration loss of the ALTERA APEX II FPGA device used earlier on the DDL SIU card is only marginally acceptable. We developed a new version of the SIU card using ACTEL ProASIC+ device based on flash memory technology. The new SIU card has been extensively tested using neutron and proton irradiation. In this paper we present the SIU card and describe the results of irradiation measurements.
        Speaker: Mr Ervin DÉNES (KFKI Research Institute for Particle and Nuclear Physics, Budapest)
        Paper
        Slides
      • 24
        The Production of the SCT Optical Links
        The on detector optical links for the SCT have been produced and mounted on the detector. Most of the off-detector opto-electronics has also been produced and has been used to successfully read out modules assembled on barrels and End Cap disks. Many problems were encountered during the production and these will be described. The lack of modularity in the system design has been a major disadvantage and some suggestions for a simpler and more modular system for the optical links for an upgraded tracker at the SLHC will be discussed.
        Speaker: Dr Anthony Weidberg (Nuclear Physics Laboratory)
        Paper
        Slides
      • 25
        Final Results of the Industrial Production of CMS Tracker Analog Optohybrids
        Approximately 15,000 analog optical transmitter modules with 2 or 3 channels each will be installed in the CMS experiment to read out the Silicon Strip Tracker. These Analog Optohybrids were produced in Austrian and Italian industries from mid- 2003 to mid-2005. After assembly, each unit was thoroughly tested for electrical and optical properties and all results are stored in the CMS Tracker database, which allows a wide range of statistical analyses. We will discuss statistical distributions of important parameters and their impact on the system. Among minor issues, three significant problems occurred during the industrial production. Those will be described together with the corrective actions taken and the lessons learned.
        Speaker: Dr Markus Friedl (HEPHY Vienna)
        Paper
        Slides
    • 15:55
      break and poster session
    • Parallel session A3
      • 26
        Mass production testing of front-end ASICs for ALICE SDD system
        This paper presents the wafer-level testing system developed for the front-end electronics of the Silicon Drift Detectors of ALICE. The system is based on a semiautomatic probe station and has been designed to test two different ASICs with minimal changes in the hardware. All the operations are controlled by a PC running a dedicated LabView software. The architecture of the test system is described and the results obtained in the mass production test are discussed.
        Speaker: Dr Luca Toscano (INFN Sezione di Torino, Italy)
        Slides
      • 27
        Production Testing and Quality Assurance of the CMS Preshower Front-end Chips - PACE3
        PACE3 is the 32-channel large dynamic range front-end amplifier, shaper and analogue memory for the CMS Preshower detector. Around 4300 PACE3, designed in 0.25micron CMOS, are required for the detector. Production of the chips has been completed and the packaged chips (fpBGA) evaluated using a custom testbench equipped with a ZIF socket under LabVIEW control. The tests are described and results presented on overall yield, digital functionality and analogue performance. Comparisons are made between chips and between wafers, as well as performance variations as a function of die position on the wafers.
        Speaker: Mr Nikolaos Manthos (University of Ioannina)
        Paper
        Slides
      • 28
        Production of the LHCb Silicon Tracker Readout Electronics
        We give an overview on the status of production of the LHCb Silicon Tracker Electronics. Lessons learned together with the industry in the preseries production of the Silicon Tracker Digitizer Boards were integrated into the design to optimize the production and assembly yield of the main batch of 700 Digitizer Boards. A report on the preseries readout module performance and on the testing procedures for the full production lot is given. In addition, a final proton irradiation test of a complete readout system has been performed, of which results will be presented.
        Speaker: Dr Achim Vollhardt (EPF Lausanne)
        Paper
        Slides
      • 29
        Microelectronic WG meeting
        Speaker: Alesandro Marchioro (CERN)
    • Parallel session B3
      • 30
        Irradiation Studies of the ATLAS Inner Detector Opto-Electronic Readout System for SLHC
        The readout system of the ATLAS inner detector for SLHC will need to cope with ten time’s higher radiation doses than the current ATLAS inner detector readout system. It is an open question of whether the current opto-electronic readout system could be used at SLHC. This is a critical question for the detector design as it will have a major influence on the layout of the readout. We have started to irradiate VCSEL lasers, PIN diodes and optical fibres up to the levels expected at SLHC and are measuring the device-performances. The results of these irradiations tests are summarized.
        Speaker: Mrs Cigdem Issever (University of Oxford)
        Slides
      • 31
        First High Fluence Irradiation Tests of Optical Link Components for Upgraded CMS at SLHC
        Lasers and photodiodes used currently in CMS, alongside new, faster components, were irradiated for the first time to very high neutron fluences, up to 2x10^16n/cm2. The usual radiation effects in lasers and photodiodes were observed, with the ultimate failure point of the device being observed for the first time. As this was a particularly aggressive test these types of components are probably still suitable for optical link applications in an upgraded experiment. Equally interesting was that the laser lifetime was limited by thermal performance as much as radiation damage. As such, both a streamlined test procedure could be envisaged in future, as well as ways to improve the device radiation resistance by better cooling.
        Speaker: Dr Markus AXER (CERN)
        Paper
        Slides
      • 32
        Performance characteristics of COTS 10Gb/s Optical Links for SLHC Experiments
        We report on the evaluation of Commercial Off-The-Shelf (COTS) optical transceivers for use in future readout and control systems of upgraded detectors for SLHC. The critical performance metrics and operational constraints on the required inputs – notably the reference clocks – will be described. Measurements of these performance metrics on samples of COTS small form-factor XFP transceivers operating at line- rates of 10Gb/s will be reported.
        Speaker: Dr Jan Troska (CERN)
        Slides
      • 33
        Optoelectronic WG meeting
        Speaker: Francois Vasey (CERN)
  • Wednesday 14 September
    • Plenary session P3

      The whole of Wednesday will be devoted to hybrids. We propose a more interactive workshop session with both talks and discussion interspersed, so the agenda should be treated as a guide. It will be updated with more details.

      • 34
        Electronics Packaging Development A never ending challenge
        There is an increased awareness in the semiconductor industry that packaging technology is an essential and integral part of the semiconductor product, and has become a critical competitive factor in many market segments since it affects operating frequency, power, reliability and costs. Costs pressure over System development investments has created a strong demand in the industry for infrastructures capable to deliver increasingly better cost- performance electronic packaging solutions. As a result of the rapidly emerging technologies and applications, the definition of exact boundaries between semiconductor, packaging and system technologies is no longer possible and all must be considered concurrently in a system-level approach to optimise the substrate design. Organic carrier technology for semiconductors devices started to be explored in the late eighties but only in the recent years these packaging development solutions started to be massively utilized as chip carriers. The majority of these technologies originated from Printed Circuit Board manufacturing processes. Under many technical aspects, organic laminates represent a great cost-performance opportunity but their utilization still requires a continuous “Adapting work” - ranging from design to materials - to the ever increasing requests from the semiconductor industry. This paper analyses the strategies used into organic packages to satisfy these constant new challenges in higher speed, power and I/O density applications.
        Speaker: Mr Stefano Oggioni (IBM Vimercate)
      • 35
        State of the art design of rigid-flex substrates – A manufacturer’s point of view
        GS Praezisions AG has been involved in the LHC project by providing electronic substrates for several experiments such as the CMS front-end hybrids, CMS Calorimeter, ALICE Silicon Pixel Detector MCM and others. Based on the experience with the designs of the various groups and countries we will highlight the common mistakes, opportunities and challenges in modern PCB design. We conclude that many design related issues can be prevented if a competent PCB manufacturer is involved at an early stage. Using proven design rules, the cost performance, manufacturability and product reliability can be significantly influenced. The authors will detail the important design rules regarding build up, choice of materials, layout and surface protection. Advantages and limitations of manufacturing methods like plasma etching and laser drilling as well as direct laser imaging will be discussed. This will help to avoid problems with implementing front end hybrids for the LHC experiments while pushing the limits of standard PCB design.
        Speakers: Mr Daniel Puschmann (GS Praezisions AG), Dr Frank Bose (GS Praezisions AG)
        Slides
    • 10:15
      break and poster session
    • Plenary session P4
      • 36
        Hybrid Design, Procurement and Testing for the LHCb Silicon Tracker
        The Silicon Tracker of the LHCb experiment consists of four silicon detector stations positioned along the beam line of the experiment. The detector modules of each station are constructed from wide pitch silicon microstrip sensors. Located at the module's end, a polyimide hybrid is housing the front-end electronics. The assembly of the more than 600 hybrids is done at industry. We will report on the design and production status of the hybrids for the LHCb Silicon Tracker and describe the quality assurance tests. Particular emphasis is laid on the vendor qualifying and its impact on our hybrid design that we experienced during the prototyping phase.
        Speaker: Prof. Frank Lehner (Zurich University)
        Paper
        Slides
      • 37
        ATLAS SCT hybrid experience
        ATLAS semi-conductor tracker (SCT) has chosen the Cu-polyimide flex circuit, reinforced with a carbon-carbon substrate for its ATLAS SCT barrel modules. We report the successes, and problems encountered and solutions, during the course of production of 2,600 pieces of the hybrid.
        Speaker: Dr Y. Unno (KEK)
        Slides
      • 38
        CMS Tracker Hybrid Experience, a user and a manufacturer perspective
        The CMS front-end hybrid project faced in the past years several difficulties which eventually brought it to the top of the CMS list of critical path items. Instead of relating the technical challenges which had to be surmounted, this presentation will attempt to find the root causes of the encountered difficulties. A CMS user and a manufacturer's point of view will make it clear that technically challenging projects can only succeed through an early and tight relationship between customer and supplier.
        Speakers: Mr Francois Vasey (CERN), Mr Hans Wyss (CICOREL SA)
        Slides
        slides2
      • 39
        CERN hybrid production experience
        The CERN TS/DEM-PMT workshop is specialised in prototype production of many types of circuits for electronic interconnection in the nuclear research field. During this talk I will present several technologies used in industry and in our workshop, ranging from standard PCBs to MultiChip Modules Deposited (MCM-D). The explanation of the production processes will be followed by an overview of the main technical problems and the limitations related to each of these technologies.
        Speaker: Mr Rui De Oliveira (CERN)
        Slides
      • 40
        Discussion
    • 12:50
      break and poster session
    • Plenary session P5
      • 41
        Quality Assurance System for the Endcap Module Hybrids of the ATLAS Semiconductor Tracker
        The quality assurance system for semi-industrial production scale of multichip hybrid circuits is presented. The hybrids are parts of the silicon strip detector modules of the Semiconductor Tracker (SCT) of the forthcoming ATLAS detector. The hybrid houses the readout and data transmission ASICs, providing the full functionality needed for binary readout of double-sided silicon strip detector modules. The hybrids are assembled in the industry using pretested components. The full quality assurance testing, including visual inspection, electrical testing and burn-in tests, is performed in the institutes of the SCT collaboration. The testing procedures and test results are presented.
        Speaker: Mr Michal Dwuznik (AGH University if Science and Technology Krakow)
        Paper
        Slides
      • 42
        ALICE SILICON STRIP DETECTOR MODULE ASSEMBLY WITH SINGLE-POINT TAB INTERCONNECTIONS
        The silicon strip detector (SSD) modules cover the two outermost layers of the Inner Tracking System of ALICE. The SSD module assembly will be performed at three locations in Europe: Helsinki, Strasbourg and Trieste. After a tedious preparation period within the whole ALICE SSD collaboration, mass production of the SSD modules was launched during autumn 2004 in Helsinki. Presently all the sites are producing the SSD modules successfully. Due to tight requirements of light structure and flexible geometry the so-called single-point tape-automated bonding (spTAB) with thin polyimide-Al cables has been chosen as interconnection technique. The technique is based on Ukrainian industrial technology. In an spTAB interconnection very reliable Al-Al bonds connect the front- end chips, hybrids and sensors together. The use of Al as conductor allows for low- force ultrasonic bonds to be performed gently at room temperature. Presently, the spTAB interconnections are performed successfully at all three sites with bonding yield approaching close to 100%. This paper describes the phases in bond process tuning before achieving this result, including discussion on the most probable root-causes of failures and the long-term reliability of the interconnections. The interconnection reliability defines the lifetime of an SSD module as a significant part of the assembly.
        Speaker: Dr Markku Oinonen (Helsinki Institute of Physics)
        Paper
        Slides
    • 15:30
      break and poster session
    • Round Table Discussion P6
  • Thursday 15 September
    • Plenary session P7
      • 43
        Pixel detectors
        Pixel detectors have replaced micro strip detectors as vertex trackers in the innermost part of collider detectors. Hybrid pixel detectors, in which sensor and read-out ICs are separate entities, constitute the present state of the art in the pixel technology being able to stand the extreme requirements at the LHC. A number of trends and further developments, most notably monolithic or semi-monolithic approaches are in development, targeting other tracking, but also imaging applications. The present state in pixel detector development as shown at the PIXEL2005 conference in Bonn, Sept. 2005 will be reviewed.
        Speaker: Dr Norbert Wermes (Physikalisches Institut)
        Slides
      • 44
        How Microelectronics could benefit the next Generation of Pixel detectors at high luminosity LHC
        Speaker: Mr Roland Horisberger (PSI)
    • 10:30
      break and poster session
    • Parallel session A4
      • 45
        System Tests of the ATLAS Pixel Detector
        The innermost part of the ATLAS (A Toroidal LHC ApparatuS ) experiment at the LHC (Large Hadron Collider) will be a pixel detector, which is presently under construction. Once installed into the experimental area, access will be extremely limited. To ensure that the integrated detector assembly operates as expected, a fraction of the detector which includes the power supplies and monitoring system, the optical readout, and the pixel modules themselves, has been assembled and operated in a laboratory setting for what we refer to as system tests. Results from these tests will be presented.
        Speaker: Dr Kendall Reeves (Uni. Wuppertal)
        Paper
        Slides
      • 46
        Performance of CMS pixel detector barrel modules
        The central part of the CMS pixel detector will consist of about 800 modules, which are mounted on three concentric barrel layers. The radii of the layers are 4cm, 7cm and 11cm. The modules cover an area of 66.5mm * 18.5mm and have 66560 pixels. The 16 Read Out Chips are connected to the sensor by bump bonds. The performance of the prototype modules has been evaluated in detail in the laboratory. Furthermore there will be a high rate testbeam at PSI to validate the performance of the module exposed to a particle rate comparable to LHC conditions. The results of the measurements from the laboratory and from the high rate testbeam will be shown.
        Speaker: Mr Christoph Hoermann (University of Zuerich/ Paul Scherrer Institut)
        Paper
        Slides
      • 47
        Pixel Multichip Module Development at Fermilab
        The efforts of the Pixel Detector R&D group at Fermilab have been concentrated on meeting the requirements of the pixel detector for the BTeV experiment. In BTeV, the pixel detector would be located close to the beam, and all collected data would be read out for use in the lowest level trigger for track and vertex reconstruction every beam crossing. We present the results of the characterization of several preproduction pixel multichip modules. These devices were characterized for threshold and noise dispersion at different operating temperatures. The pixel modules were tested for bump-bond connectivity and calibrated with an X-ray source.
        Speaker: Mr Marcos Turqueti (Fermilab)
        Paper
        Slides
      • 48
        Concept, realization and characterization of serially powered pixel modules
        We demonstrate here for the example of the large scale pixel detector of ATLAS that Serial Powering of pixel modules is a viable alternative powering scheme that have been devised and implemented for the modules using dedicated on-chip voltage regulators and modified flex hybrid circuits. The equivalent of a pixel ladder consisting of six serially powered pixel modules with about 0.3 Mpixels has been built and the performance with respect to noise and threshold stability and operation failures has been studied. We believe that Serial Powering in general will be necessary for future large scale tracking detectors.
        Speaker: Mr Duc Bao Ta (Rheinische Friedrich-Wilhelms Universität Bonn)
        Paper
        Slides
      • 49
        Study of serial powering of ATLAS silicon strip sensors
        Serial powering of silicon detectors can dramatically reduce the number of power cables. This will relax space constraints, reduce material, and minimize power losses in cables. A study of the power efficiency of a serial powering scheme for silicon strip detector modules is performed. Numerical results are presented as a function of the number of modules, supply voltage, and cable resistance. Serial powering results in a significantly higher power efficiency than a conventional parallel powering scheme for typical particle physics applications. First tests with four ATLAS SCT silicon strip modules powered in series show encouraging results.
        Speaker: Dr Marc Weber (Rutherford Appleton Laboratory)
        Paper
        Slides
    • Parallel session B4
      • 50
        ATLAS DAQ/HLT infrastructure
        The ATLAS DAQ/HLT equipment is located in the underground counting room and in the surface building. The main active components are rack-mounted PC's and switches. The issues being resolved during the engineering design are powering and cooling of the DAQ/HLT equipment, monitoring of the environmental parameters, installation and maintenance procedures. This paper describes the ongoing activities and presents the proposed solutions.
        Speaker: Dr Yuri ERMOLINE (MSU)
        Paper
        Slides
      • 51
        The VMEbus processor hardware and software infrastructure in ATLAS
        Most of the off-detector custom electronics of the ATLAS data acquisition system such as the Read-Out Drivers or the Trigger and Timing Control system has been implemented in VMEbus. The paper describes the process of selecting a common VMEbus processor module for all VMEbus systems in ATLAS and the problems encountered during the evaluation of different candidate cards. Some performance figures for VMEbus transfers are presented. The paper also discusses why ATLAS has decided to develop its own Linux based VMEbus driver and presents the features and performance of that driver and its user level library as well as some related software packages.
        Speaker: Mr Markus Joos (CERN)
        paper
        slides
      • 52
        A High Voltage System with 60 High Voltage Power Supply Channels in 2U Height EURO Crate
        A high voltage system includes 60 high voltage power supply channels in a 2U height EURO crate. The system is interfaced with a computer through USB interface. The output voltage of the channel ranges from 1 kV to 4 kV with an output current of more than 100 uA. Ripples on the output voltage is less than 100 mV in peak-to-peak amplitude. The output voltage can be set and monitored with 1 V resolution. The output current is monitored with 9-bit resolution at the sampling rate of 80 Hz. The channel is provided with over-current shut-down. A hardwired logic turns off the output voltage when the output current exceeds a prescribed limit current in a predefined time interval, where the limit current and the time interval can be set by the computer. Since high voltage is generated by a ceramic transformer, the system can be operated in a magnetic field of 1 T. The high voltage system satisfies the CERN Radiation Hard Criteria required for TGC power supplies.
        Speaker: Masaya ISHINO ((International Center for Elementary Particle Physics (ICEPP), University of Tokyo))
        Paper
        Slides
      • 53
        Electromagnetic Compatibility of a DC Power Distribution System for the ATLAS Liquid Argon Calorimeter
        The front end electronics of the ATLAS Liquid Argon Calorimeter is powered by DC/DC converters nearby the front-end crates. They are fed by AC/DC converters located in a remote control room through long power cables. The stability of the power distribution scheme is compromised by the impedance of the long interconnection cable, and proper matching of the converters dynamic impedances is required. Also, the long power cable fed by a powerful AC/DC converter is a source of electromagnetic interferences in the experimental area. The optimal grounding and shielding configuration to minimize these EMI is discussed.
        Speaker: Mr Georges Blanchot (CERN)
        Paper
        Slides
      • 54
        Compact Data acquisition and Power supply system designed for hostile environment condition concerning radiation and magnetic field
        A compact data acquisition and power supply system housed in a water cooled special crate has been designed for the readout of the TOF (Time Of Flight) detector of the Alice experiment at CERN. The Crate contains a 12 slot VME64X bus that houses 2400 multi-hit 25ps TDC channels (TRM), a Trigger Module (LTM), a Clock Distribution Module (CPDM) and a data readout manger (DRM board) with two optical links and Ethernet. The same crate hosts the branch controlled power supply modules for the VME boards and the TOF detector front-end modules. The whole system shall be used close to the TOF detector and will work under moderate magnetic field and radiation (5 KGauss, 1.2 Gy/10 years TID). The TDC boards house TDC chips developed by CERN/ECP-MIC Division (HPTDC). Due to the radioactive environment, an accurate choice of components is required and the VME boards implement protections from Single Event Latch-up and from Single Event Upset.
        Speaker: Mr Stefano Petrucci (CAEN CAEN S.p.A., Via Vetraia 11, Viareggio, Italy)
        Slides
    • 13:05
      break and poster session
    • Parallel session A5
      • 55
        The Front-End Electronics System for the CMS Electromagnetic Calorimeter
        CMS designed an high precision electromagnetic calorimeter, to be operated reliably in the high radiation environment of the CERN Large Hadron Collider (LHC), inside the 4 T magnetic field. Innovative solutions were developed to place the front-end electronics within the detector with the advantage of minimizing external noise, while reducing the number of optical links to send data to the off-detector readout. The final system architecture will be reviewed in detail.High resolution, over the wide energy dynamic range, was obtained with studies in an electron test beam.
        Speaker: Mrs Nadia Pastrone (I.N.F.N. Torino)
        Paper
        Slides
      • 56
        Installation and Test of the CMS Crystal Calorimeter Electronics
        The CMS Electromagnetic Calorimeter consists of roughly 76000 lead tungstate crystals. Nearly 25000 Printed Circuit Boards of 5 different types and about 5500 Gigabit Optical Links are used to process the signals of the photo-detectors and to send the resulting data to the off- detector electronics. The integration of this electronics together with its cooling system, mechanical supports, the low voltage distribution, various signal cables and optical fiber patch panels is described. Complexity and installation sequence require tests at each step of installation. The test strategy during the installation is described and results of the system performance achieved are presented.
        Speaker: Mr Werner Lustermann (Eidgenoessische Technische Hochschule, ETH Zurich, Switzerland)
        Paper
        Slides
      • 57
        CMS ECAL Front-End boards: the XFEST project
        The Front-End (FE) boards are part of the on-detector electronics system of the CMS electromagnetic calorimeter ECAL. Their numerical functionalities and properties are tested by a dedicated test bench located at Laboratoire Leprince-Ringuet, prior to the board integration in the CMS detector at CERN. XFEST, acronym for eXtended Front-End System Test, is designed to perform tests that can last several hours, on up to 12 FE boards in parallel. The system is foreseen to deliver 80 tested boards per week. This contribution presents the XFEST set-up and the results of the measurements on FE boards.
        Speaker: Caroline Collard (LLR Ecole Polytechnique)
        Paper
        Slides
      • 58
        The Readout, Fast Control and Powering Architecture for the CMS Preshower
        The CMS Preshower detector (ES) comprises ondetector and offdetector components of the readout and control system, as well as the powering system and optical links. The fast control system is largely built around the one originally conceived for the CMS Tracker (FEC, DOH, CCU etc.) whilst the readout part profits from developments made for the CMS ECAL (DCC, GOH, AD41240). There are two ESspecific ASICs: PACE3 (frontend preamp/ shaper/analogue memory) and Kchip (data concentrator). Two custom ondetector PCBs have also been developed: the frontend hybrid (containing the PACE) and the system motherboard (containing all power regulators, digital chips, optical components and ADCs). The full architecture is presented, along with results from system tests.
        Speaker: Mr Wojciech Bialas (CERN)
        Slides
      • 59
        Characterization and production testing of a quad 12 bit 40 Ms/sec A/D converter with automatic digital range selection for calorimetry.
        The AD41240 is a custom made 12-bit 40 MSPS, quad-channel, radiation tolerant analog- to-digital converter for the front-end readout electronics of the CMS ECAL and Preshower detectors. The A/D converter features a special digital circuitry to allow automatic selection of gain ranges when it is used with a multi gain pre-amplifier. This paper describes the design architecture of the A/D converter as well as the characterization methodology that has been employed to access its performance. It presents also the production testing procedures that were carried out on a specially designed testbench capable to perform full DC and dynamic tests on packaged parts in about 10 seconds per chip. A total number of 100,000 components will need to be tested. Cumulative results are reported on yield and performance based on data acquired during the production testing of 50,000 components.
        Speaker: Dr Kostas Kloukinas (CERN)
        Slides
    • Parallel session B5
      • 60
        Progress with the CMS Tracker control system
        The recent progress on the CMS Tracker control system is reviewed in depth, with a report of activities and results related to ongoing parts production, acceptance testing, integration and system testing, as well as controls software development. The integration of final parts into Tracker systems and the subsequent testing is described taking the Tracker Outer Barrel as an example application.
        Speaker: Mr Karl Aaron Gill (CERN)
        Paper
        Slides
      • 61
        The Detector Control System for the ALICE Time Projection Chamber Front-end electronics
        The ALICE Time Projection Chamber (TPC) is read out by 4356 Front-End Cards serving roughly 560000 channels. Each channel has to be configured and monitored individually. As one part of the overall controlling of the detector this task is covered by the Detector Control System (DCS). Since fault tolerance, error correction and system stability in general are major concerns, a system consisting of independently running layers has been designed. The functionality layers are running on a large number of nodes and sub-nodes. This talk will focus on the concept and architecture of the DCS for the Front-end electronics of the Time-Projection Chamber (TPC) and present results and experiences from system integration tests.
        Speaker: Mr Matthias Richter (University of Bergen, Dep. of Physics and Technology)
        Paper
        Slides
      • 62
        Design and performance of the front-end electronics of the LHCb Muon Detector
        The system architecture of the front-end electronics of the LHCb Muon Detector, consisting of wire-chamber detectors and, for a small region, of triple-GEM detectors, is reviewed. The design of the front-end boards and of the ASD chip, the CARIOCA and the CARIOCA-GEM, are discussed in detail, together with the performances measured both with test benches in the lab and on chamber with radioactive sources and cosmic ray stands. The status of the production and the testing procedures of the 8,000 boards and the 24,000 chips, built with the 0.25mm radiation tolerant technology, will also be summarized.
        Speaker: Dr walter Bonivento (INFN CAGLIARI, Italy)
        Paper
        Slides
      • 63
        Advanced Front End Signal Processing Electronics for ATLAS CSC System: Status and post production performance.
        The ATLAS muon spectrometer will employ Cathode Strip Chambers (CSC) to measure high momentum muons in the extreme forward regions [1]. Preamplification of the charge on the strips is performed in the Amplifier Shaper Module I. Amplifier Shaper Module II performs the analog buffering, digitization of the charge signals from individual cathode strips and multiplexes the data into two fiber optics links running at 1 Gbps each. We present the design architecture of the complete front end electronics chain and its performance. We also report on the production and testing status of overall on detector electronics.
        Speaker: Mr Sachin Junnarkar (Brookhaven National Laboratory)
        Slides
      • 64
        Performances of the Coincidence Matrix ASIC of the ATLAS Barrel Level-1 Muon Trigger
        The ATLAS Barrel Level-1 muon trigger handles data coming from the Resistive Plate Chamber detectors, structured in three concentric layers inside the air-core barrel toroid. The trigger classifies muons within different programmable transverse momentum thresholds, and tags the identified tracks with the corresponding bunch crossing number. The algorithm looks for hit coincidences within different detector layers inside the programmed geometrical road which defines the transverse momentum cut. The Coincidence Matrix ASIC implements the trigger algorithm and the readout of the RPC detector, processing hit signals coming from up to four detector layers. It finds muon track candidates and generates the output trigger patterns within a latency of a few 25 ns bunch crossing periods, and produces and time tags the readout hit patterns. Due to the different performance needs and limitations in the technology, the CMA input pipeline and trigger logic and the time interpolator run at the working frequency of 320 MHz, the readout part works at 160 MHz while the control part works at 40 MHz. Performances of the ASIC have been studied on different test station, the test results are presented.
        Speaker: Mr Riccardo Vari (Istituto Nazionale di Fisica Nucleare (INFN))
        Paper
        Slides
    • 16:05
      break and poster session
    • Parallel session A6
      • 65
        End-Ladder Board for ALICE SDD Experiment
        The paper presents an end-ladder card prototype of the data acquisition chain of the ALICE SDD experiment. The prototype includes most of the electronics devices that will be applied to ALICE SDD experiment. The card interfaces with the front-end electronics and with the counting room detector data link. It has been designed taking into account the constraints on the dimensions of the final apparatus. It has been fully tested within the data acquisition chain and, since the results were good,the final design for production is close to submission.
        Speaker: Dr Alessandro Gabrielli (INFN & Physics Department of Bologna University)
        Paper
        Slides
      • 66
        Evolution of the TRT backend and the new TRT-TTC board
        The Transition Radiation Tracker, made of 370’000 cylindrical straws, is a combined tracking and electron identification detector, part of the ATLAS Inner Detector at CERN’s LHC. The back-end electronics, which are in charge of the communication with the front-end boards mounted all around the detector, are made up of two types of 9U VME boards. One type is the ROD boards, collecting, compressing and synchronising data from the front-end electronics. The second type is the TRT-TTC boards, transmitting the timing, trigger and control signals to the on-detector electronics using a special protocol. The current back-end of the TRT and its evolution will be presented, as well as the new TRT-TTC board.
        Speaker: Mr Peter LICHARD (CERN)
        Paper
        Slides
      • 67
        SPD Very Front End Electronics
        The SPD (Scintillator Pad Detector) is a part of LHCb calorimetry. Its function is to discriminate between charged particles and neutrals for the LHCb level0 trigger. This detector uses scintillator pad readout by wavelength shifting (WLS) fibbers that are coupled to MAPMT via clear plastic fibbers. The specific features of the SPD detector are the high granularity in the inner part of the detector, and the use of 64-channel photomultiplier tubes with small pixel dimension. The choice of a MAPMT allowed to design a fast, multi-channel pad detector with a reduced cost per channel.. The signal outing the SPD PMTs has large fluctuations in the signal pulse shape since the average of photoelectrons is only about 20-30 due to the response of the WLS fibre, which has low decay time. This fact causes another bothering trouble: the potential tail of a high amplitude event could cross the threshold and provoke a fake trigger. Thus, pile-up correction is needed. SPD Readout system is performed by an specific ASIC which integrates the signal, makes the pile-up compensation, and compares the level obtained to a programmable threshold (distinguish electrons and photons), an FPGA which programmes the ASIC threshold and pile-up subtraction and finally LVDS serializers, in order to send information to the first level trigger system.
        Speaker: Mrs Sonia Luengo (La Salle, School of Engineering, Universitat Ramon Llull)
        Paper
        Slides
    • Parallel session B6
      • 68
        A multiplicity trigger based on the Time of Flight detector for the ALICE experiment
        The goal of the ALICE Time of Flight detector, based on MRPC technology, is to perform charged particle identification at |eta|<1. This large area (150 m^2), finely segmented detector (~160,000 channels), provides fast signals which will contribute to the L0 and L1 trigger decisions. Hits from the TOF detector are used to determine the multiplicity and topology of the events. This information is used to (a) generate a cosmic muon trigger and (b) to differentiate between central and peripheral collisions. The system architecture foresees a first layer of 72 VME boards interfacing the detector front-end to a second layer, which receives and processes all the information and takes trigger decisions.
        Speaker: Dr Eugenio Scapparone (infn - Bologna)
        Paper
        Slides
      • 69
        ALICE TRD Track Matching Unit with 12 Multi-Gigabit Inputs
        The ALICE TRD trigger demands for high-speed computation and low-latency transmission of event data along the complete data path. The module presented here is being developed for the detector's global online tracking unit which contributes to the L1 trigger of the experiment. It is an FPGA-based system utilizing PCI and 12 fibre-optical SFP transceiver interfaces, realized as a CompactPCI plug-in card. Three independent 8-Bit wide source synchronous LVDS interfaces allow for low-latency connection to other modules. The main FPGA is a Xilinx Virtex-4 FX chip which includes integrated multi-gigabit serializer/deserializer and PowerPC processor blocks. Three 36-Bit wide QDR2-SRAM chips provide a high-bandwidth memory used as event buffer.
        Speaker: Mr Jan de Cuveland (University of Heidelberg)
        Slides
      • 70
        Trigger Region Unit for the Alice PHOS calorimeter
        The electromagnetic Photon Spectrometer (PHOS) of ALICE measures electromagnetic showers up to 100 GeV with PbWO4 crystals and APD's placed a cold zone of -25 C. Readout regions of 448 crystals are combined as coherent trigger regions via analog signals which are processed by one FPGA-based, Trigger Region Unit (TRU). The signals are 2*2 analog sums with 100 ns shaping time, connected over equal length flat cables from 14 FEE digitizer boards to a centrally placed TRU board with an FPGA which receives all signals from the trigger region after 8 bit, 40 MHz conversion. Both level-0 and level-1 trigger algorithms are executed within the FPGA, consisting on charge summing over sample times and over 4*4 crystal windows. Due to external latencies, the level-0 decision is due after 300 ns processing time, whilst 5 us are available for more refined level-1 decisions. The trigger outputs are transmitted as 40 MHz Yes/No signals to the central trigger processor. The 10 layer TRU cards have been designed around a 50 kilogate Xilinx VirtexPro FPGA, with external reconfiguration logic, allowing to detect and correct single event upsets during operation. In view of further applications in Alice, the TRU is equipped with a level-0 multiplicity input and 1 Gbit/s serial outputs for building hierarchies of TRU triggers. Eight TRU cards are embedded together with 112 FEE cards inside the closed PHOS modules, necessitating water cooling for both TRU and FEE cards via surrounding copper cassettes.
        Speaker: Mrs Alexandra Oltean
        Paper
        Slides
      • 71
        Beam Phase and Intensity Monitor for the LHCb experiment
        The LHC RF clock is transmitted over kilometres of fibre to the experiments where it is distributed to thousands of front-end electronics boards. In order to ensure that the detector signals are sampled properly, its long-term stability with respect to the bunch arrival times must be monitored with a precision of <100ps. In addition it is important to monitor the LHC bunch structure and the trigger conditions by measuring the intensity of each bunch locally in the experiment. For this purpose a beam phase and intensity acquisition board (BPIM) is being developed for the Button Electrode Beam Pickups which will be installed on both sides of all the LHC interaction points. The board measures the two quantities per bunch, and processes and histograms the information in an onboard FPGA. The information is read-out by the Experiment Control System and directly fed to the LHCb Timing and Fast Control system.
        Speaker: Dr Richard Jacobsson (CERN)
    • 19:00
      DINNER
  • Friday 16 September
    • Plenary session P8
      • 72
        Implementing Artificial Neural Networks in Mixed-Mode VLSI
        This talk presents different VLSI models of artificial neural networks ranging from abstract ones using binary neurons to biologically inspired pulse-coupled systems. Circuit examples demonstrating common design principles for optimizing area usage and network speed are shown. The usage of digital communication protocols allows the parallelization of the analog network cores to create large-scale artificial network systems. A key aspect of neural network research is training. Specific training algorithms for simple and complex electronic neuron models have been investigated. For binary models, evolutionary- as well as liquid-computing has proven to be successful. While these methods operate on a global level, the pulse-coupled systems use a local learning rule inspired by contemporary neuroscience called 'spike time dependent plasticity' (STDP). Therefore the VLSI system allows the investigation of important aspects of natural neural plasticity at a speed several orders faster than biological real time.
        Speaker: Prof. Joannes Schemmel (Kirchhoff Institut fuer Physik / Electronic Vision(s))
      • 73
        Recent Progress in Field Programmable Gate Arrays
        In step with Moore’s Law, FPGAs are continuing their rapid progress. IC technology makes circuits smaller and faster, while 300 mm wafers with low defect density reduce the cost. Innovative chip structures support adaptation to conflicting user demands, and combine with flip-chip packaging to improve the electrical characteristics. This paper describes several new or enhanced dedicated sub-circuits that improve density and performance, and often reduce power consumption. The growing user community expects better tools, larger core libraries, and competent technical support. FPGAs have found their way into most digital systems and increasingly also into cost-sensitive consumer applications.
        Speaker: Dr Peter ALFKE (Xilinx, Inc. San Jose, CA, USA)
        Slides
      • 74
        FPGA Dynamic Reconfiguration in ALICE and beyond
        Using the FPGA Virtual File System for Dynamic Reconfiguration of FPGAs, we have been investigating improvements to various aspects and components of the ALICE electronics. In this paper, we will briefly summarize the results from our work on improving the radiation tolerance of FPGA-based experiment electronics, followed by a deeper coverage of our more recent work on using the File System for reconfiguration of functional modules and for FPGA debugging, including the underlying concepts as well as the practical applications for ALICE and LHC in general.
        Speaker: Mr Gerd Troeger (Kirchoff-Institut fuer Physik, Universitaet Heidelberg)
        Paper
        Slides
    • 10:35
      break
    • Plenary session P9
      • 75
        TTC challenges and upgrade for the LHC
        The TTC (Timing, Trigger and Control) system broadcasts the timing signals from the LHC machine to the experiments. At the detector level, it integrates the trigger information and local synchronous commands with these signals, for transmission to several thousands of destinations. If the support of the TTC system at the level of the detectors is well in hand, the main network between the machine and the experiments will require re-development to ensure its easy maintenance. A status of this system will be presented, as well as the challenges it has to cope with and the necessary upgrade which will be needed in the near future to make it operational for LHC start in 2007.
        Speaker: Mrs Sophie BARON (CERN)
        Paper
        Slides
      • 76
        A Tracking Detector for Triggering at SLHC
        We report on preliminary design studies of a pixel detector for CMS at the Super-LHC. The goal of these studies was to investigate the possibility of designing an inner tracker pixel detector whose data could be used for selecting events at the First Level Trigger. The detector considered consists of two layers of 50x50 m2 pixels at very close radial proximity from each other so that coincidences of hits between the two layers amount to a track transverse momentum cut. This cut reduces the large amount of low momentum data expected at SLHC whilst it keeps the tracking efficiency very high for high transverse momentum tracks
        Speaker: Mr John Jones (Imperial College London)
        Paper
        Slides
      • 77
        Swift integrated signal processing architectures for CMOS sensors equipping future vertex detectors.
        Monolithic Active Pixel Sensor (MAPS) using standard low cost CMOS technology available from industrial manufacturers, have demonstrated excellent tracking performances for minimum ionising particles. The need for highly granular, thin and radiation tolerant pixel arrays equipping the vertex detector foreseen at the future International Linear Collider (and elsewhere) drive an intense R&D effort, aiming to optimize the intrinsic sensor performance and to obtain an appropriate swift and low noise electronics architecture for on-chip data processing. Besides this main issue, work on radiation tolerance and backthinning of the sensors is under way. The state of art of these developments will be exposed, emphasizing the main micro-circuit architectures under study and their critical design issues.
        Speaker: Mr Sébastien HEINI (IReS laboratory)
        Slides
      • 78
        CLOSE OUT
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