Speaker
Description
Summary
The CMS silicon Preshower is a fine grain detector placed in front of the endcap
Electromagnetic calorimeter. Its primary function is to detect photons with good
spatial resolution in order to perform π0 rejection. The detector comprises around
4300 silicon sensors, each measuring 6.3cm x 6.3cm divided into 32 strips, with
strip capacitance in the region of 50 pF. Each sensor is attached to a single PACE3
front-end chip, which performs amplification and shaping of the signals from the
silicon, followed by voltage sampling into an on-chip analogue pipeline memory 192
cells deep.
PACE3 is composed of two separate ASICs called Delta and PACE-AM. Delta performs the
amplification and shaping and can operate in two gain modes: high gain (HG) for
calibration with single minimum ionizing particles (MIPs: 1 MIP=3.6fC) and low gain
(LG) for normal physics running where a high dynamic range is required (1-400 MIPs).
PACE-AM is the analogue memory, FIFO and output multiplexer etc. and includes a
large amount of digital logic. Upon reception of a trigger signal, three memory
locations (containing the sampled analogue signals from the sensors) are blocked
and their addresses written to a FIFO. The data readout is asynchronous with the
trigger. Up to 16 triggers can be stored in the memory without overflowing the
FIFO.
Both ASICs are packaged in single 196-pin 1mm-pitch fpBGA. Each chip incorporates a
number of registers and DACs, programmable via i2c. These include registers that
hold unique laser-blown identifiers (IDs) for every ASIC. The IDs contain
information on production lot, wafer number, reticle position and chip position
within the reticle.
Fast timing/trigger signals are supplied via LVDS.
The packaged chips are tested using a custom testbench equipped with a ZIF socket
under LabVIEW control. A large number of digital tests are performed, including scan
chains, tests of all bits in all registers, the skipping mechanism, the blocking and
unblocking of memory locations etc.
The response of the PACE3 to reset signals is tested, along with measurements of
power consumption in “sleep” and “run” modes.
A programmable amplitude internal injection signal is provided and used to test each
readout channel (and measure channel-to-channel variations). This injection signal
also allows the measurement of dynamic range, signal-to-noise and, coupled with a
programmable delay circuit (provided on the testbench), the timing characteristics.
The PACE3 programmable latency facilitated the measurement of memory uniformity.
The absolute analogue performance of the PACE3, in terms of noise, timing and
dynamic range, depends significantly on the Delta input capacitance – i.e. the
presence or not of the silicon sensor. For these tests no sensor was present, so a
qualitative analysis only could be performed (The good chips are subsequently
mounted on PCBs and bonded to sensors. At this stage a quantitative analysis of the
analogue performance is made), but this was sufficient to be able to find
pathologically bad chips.
The main components of the testbench were an FPGA – to provide LHC-like fast timing
and control signals, and a microcontroller – for slow control via i2c and data
readout through an on-board 12-bit 40 MHz ADC. The testbench was connected via RS232
to a commercial PC running dedicated LabVIEW software. The chip IDs are used to
create data directories that store the results of each test. These files, about
300kbytes per PACE3, are subsequently sent to the CMS ECAL Construction Database –
CRISTAL. In addition, summary files are also produced by the software and stored in
CRISTAL. The complete set of tests takes around 3 minutes per PACE3.
Many thousands of chips have now been evaluated, from an initial engineering run (2
wafers, providing ~600 chips) and a subsequent production run (48 wafers). The yield
has been measured to be better than 80%. A majority of the failures are due to
short-circuits that result in no possible communication to the chip. This was easily
(and quickly) identified due to out-of-spec power-on consumption. A few percent of
chips exhibited problems with the digital functionality; for those passing only a
tiny fraction exhibited out-of-spec analogue performance. Indeed the analogue
performance is extremely uniform between chips and wafers.
