Speaker
Description
Summary
Three pillars of progress:
1. Technology, 2. Architecture and Circuits, 3. Software and IP.
Technology:
90 nm CMOS technology on 300 mm wafers with ultra- low defect density. A third,
intermediate gate oxide thickness reduces leakage current.
Thin oxide for the 1.2 V core logic ( fast, but high leakage).
Medium oxide for configuration storage and pass transistors (slower, but much lower
leakage).
Thick oxide for I/O circuits with Vcc = 2.5 to 3.3 V.
ASMBL (Application Specific Modular Block Architecture) arranges specific circuit
elements in specific vertical columns. Lets chip design and software create sub-
families with a different mix of logic, BlockRAMs, multiplier-accumulators,
microprocessors and multi-gigabit transceivers. I/O is now distributed, good for
flip-chip packaging. Each I/O pin has adjacent ground and Vcc balls for a smaller
return-current inductive loop, thus reducing ground bounce and ringing.
Architecture and Circuits:
Fast, expandable 48-bit adder/accumulator with 18 x 8 multiplier input uses
significantly less power. Can be concatenated for up to 48-tap FIR filtering, while
maintaining 500 MHz speed. Can also be used as a fast 36-bit adder, register, or
counter, and the multiplier can be used as a barrel shifter.
Dual-ported BlockRAM expandable to 512 x 72 bits with Hamming error correction.
Built-in FIFO controller can be clocked at up to 500 MHz from independent write and
read clocks. Asynchronous arbitration for FULL and EMPTY and
programmable “dipstick”. Optional fall-through mode for first data entry.
ChipSync Input/Outputs:
Today’s high-speed I/O must use clock-forwarding or Source Synchronous clocking,
routing the clock together with the data. Operates up to 1 Gbps, but requires that
clock and data be properly aligned at the receiver. The ChipSync structure,
available on every Virtex-4 pin, provides a programmable delay with stable 75 ps
granularity, intended to align the clock exactly with the data eye opening.
ChipSync on each pin also acts as serial-to-parallel and parallel-to-serial data
converter and appropriate clock divider It supports word alignment through its
Bitslip feature.
ChipSync can also be used to measure incoming pulses with 75 ps precision.
Multi-Gigabit Transceivers:
Serial data-communication demands speeds of up to 11 Gbps. The Virtex-4 MGTs
convert between 32/40 bit parallel data @ up to 300 MHz and serial I/O @ up to 11
Gigabits/sec. Self-contained transceiver blocks have programmable FIFOs, 64B/66B
code converters, output pre-emphasis and input equalization, able to communicate
directly over 40 inches of pc-board backplanes.
Microprocessor and Ethernet Controller
One or several industry-standard PowerPCs are integrated into the FPGA fabric, can
use their instruction and data caches for ultra-compact controller applications, or
use BlockRAm or external RAM.
Software and Intellectual Property:
200,000 users demand capable, efficient and user-friendly tools for synthesis,
placement and routing, and for design simulation and debugging. They also expect
extensive libraries and validated cores to choose from, as well as competent and
timely support by hotline engineers, by field applications engineers and in user
newsgroups.
FPGAs have come a long way, and now provide vital subsystem solutions in most
digital systems, even in cost-sensitive high-volume applications.
