Speaker
Description
Summary
The APV25 is the 128 channel chip for CMS silicon tracker readout, manufactured on
200 mm wafers in 0.25 micron CMOS technology. A high yield of multi-chip hybrids
for detector modules requires comprehensive testing of chips on the wafer.
Each APV channel comprises a low noise front end, a 50 ns CR-RC shaping amplifier,
a 192 element deep analogue pipeline, and an analogue pulse shape processing stage
(APSP). The pipeline samples the amplifier output at 40 MHz and accommodates the
level one trigger latency and buffering of events awaiting readout.
The APSP implements a deconvolution operation on 3 consecutive pipeline samples to
achieve single bunch crossing resolution at high luminosities. Analogue output
samples are multiplexed onto a single output for subsequent optical transmission
to the off-detector data acquisition system. The chip contains system features
including bias and calibration pulse generation, programmed via the slow control
interface. The on-chip programmable features enable a thorough wafer probe test to
be performed leading to a high level of confidence in identifying defective chips.
Approximately 75,000 chips (plus spares) were required to read out approximately 10
million microstrip channels. Wafers were delivered in production lots of up to 25
wafers, each wafer containing 360 viable APV sites. We have previously reported
[1,2] on progress and problems encountered during the several years over which this
production task has been spread. Because of wafer yield and hybrid production
losses we have probe-tested more than 500 wafers (180,000 chips) to obtain
sufficient numbers of APVs to complete the tracker construction.
The on-wafer chip tests included detailed verification of both digital and analogue
functionality. Digital tests included verification of the slow control interface,
and correct operation of the pipeline control logic, and any defect here resulted
in rejection. Analogue tests included pedestals, pulse-shape, gain and noise
measurements, pipeline uniformity, individual pipeline element storage capability,
and power consumption. Performance was verified in all operational modes for all
channels. Analogue acceptance thresholds were defined to ensure satisfactory
performance for the application. A test time/chip close to one minute, allowed a
throughput of 2 wafers/day. All the wafers were tested on a single semi-automatic
probe-station.
During testing all chips were identified by wafer name and location on the wafer,
maps being produced for subsequent dicing and picking by the hybrid manufacturer.
The test results were stored in a database, allowing us to perform detailed
analyses comparing performance between chips, wafers and production batches.
The results of these analyses provide insight into the stability of performance
achievable from a large-scale manufacturing task extended over several years.
[1] APV25 Production Testing and Quality Assurance, M.Raymond et al, Proceedings of
the 8th workshop on electronics for LHC experiments, CERN-LHCC-2002-34, 219-223.
[2] Production Testing and Quality Assurance of CMS Silicon Microstrip Tracker
Readout Chips, P.Barrillon et al, Proceedings of the 10th workshop on electronics
for LHC experiments, CERN-LHCC-2004-030, 148-152.
