Speaker
Description
Summary
The LHCb muon detector is approaching the installation phase of all its subsystems
and adequate test coverage of all parts and units is a key requirement. A testing
station based on cosmic rays can prove to be an invaluable tool to point out
performance issues and to perform a highly accurate quality control of chambers
tested. It allows control of operation of elements like Front-End Boards and the
Experiment Control System, evaluating efficiency and time resolution of fully
assembled units.
We designed an apparatus in order to receive data from, and to control in parallel
six chambers, all fitted with Front-End Boards and generating a total of 576
channels to be read with a 128-channel multi-hit TDC. In order to perform track
reconstruction for muons crossing the 6 chambers, all signals must be read at the
same time, calling for time multiplexing in order to reduce the number of lines.
Applying selected multiple amounts of delay to channels, joining and sending them
to a multi-hit TDC module, is how time multiplexing is carried out.
A fundamental parameter in the LHCb muon detector is time resolution: MWPCs have
been designed in such a way as to maintain detection efficiency higher than 99%
within the 25ns LHC bunch crossing period, with a time resolution of the order of
3ns. For this reason delay granularity has been set to a value of 100ns, thus
avoiding overlaps of data belonging to different events. Jitter caused by the delay
lines can worsen time resolution of measurements: the total value of all
contributions should remain below 1ns. Jitter evaluation on devices showed a total
contribution of about 800ps to the total figure. Results of measurements will also
be included.
Multiplexers are 6U 12HP modules, with four programmable logic devices (Xilinx
Spartan IIe XCV300) on board, and are based on an 8-layer printed circuit. On-board
FPGAs are capable of applying selected delays to channels via a custom designed
macrocell, which is replicated inside the device. Disabling selected channels is a
beneficial feature in case of noise or faults, and it is made possible by an I2C
interface implemented on each FPGA. Each Multiplexer is capable of receiving 128
logical channels and of merging them into 32, before their final transmission to a
multi-hit TDC.
The testing station uses four Multiplexers, each receiving signals from chambers
fully instrumented with Front-End cards (called CARDIAC); its trigger system is
based on two layers of scintillators with a contribution to total jitter of 2ns.
Such an apparatus has been assembled and is currently utilized as a last stage in
performance evaluation. Fully instrumented chambers in groups of six are tested
with no significant deterioration of time resolution and the system can function as
a fully operational readout system for a maximum of 576 channels in spite of its
small scale and low cost.
