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Summary
Submicron CMOS technologies provide well-established solutions to the
implementation of low noise front-end electronics for a wide range of detector
applications. The advantages in the design of high performance mixed signal systems
were exploited in recent years and led to the fabrication of integrated circuits in
0.35 um and 0.25 um CMOS processes. Following the trend of commercial silicon
foundries, the IC designers’ effort is gradually shifting to 0.13 um CMOS
generations, to implement readout integrated circuits for silicon strip and pixel
detectors, in view of future applications (LHC upgrades, Linear Collider, Super B-
Factory). Furthermore, a beneficial side effect of CMOS scaling is that the
technology becomes harder for every new generation. This observation is related to
the thickness reduction of both the gate and isolation dielectric layers, making
them less susceptible to ionization damage. However, it is very important to assess
the impact of technology scaling on the noise parameters, which can be affected by
gate oxide quality and short-channel phenomena. This can be very critical in
applications such as LHC upgrades, where a very short signal shaping time is
required because of high event rate, or where a thin silicon detector (100 um or
less) is mandatory for material minimization or radiation hardness.
The MOSFETs studied in this paper belong to two commercial CMOS processes with
minimum gate length of 0.13 um and manufactured by STMicroelectronics and IBM. The
devices were characterized at drain currents from several tens of uA to 1 mA, that
is, the usual operating currents of input devices in integrated charge-sensitive
preamplifiers. In these conditions, deep submicron devices are biased in weak or
moderate inversion. The behavior of the 1/f and white noise terms is studied as a
function of the device polarity and of the gate length and width to account for
different detector requirements. The analysis of the experimental results includes
the comparison of PMOS and NMOS inside the 0.13 um CMOS generation considering
devices from the two foundries.
In this study an evaluation of the impact of ionizing radiation on the analog
performances is also reported and discussed. An interesting point is to verify if
standard open structure devices can be safely used in rad-hard circuits, without
implementing any special radiation hard technique. Besides key parameters, such as
the threshold voltage shift, a special attention is given to the beavior of white
and 1/f components in the noise voltage spectrum. Experimental results point out
that open structure devices in the examined 0.13 um technologies exhibit a large
degree of tolerance to ionizing radiation. This may be exploited to remove geometry
constraints and increase functional density.
