11th Workshop on Electronics for LHC and future Experiments

SWIFT: A Deskewing and Fault Tolerance Switch for LVDS Links

Not scheduled

1m

Heidelberg

Poster Custom Integrated Circuits

Speaker

Dr Gloria Torralba (Kirchhoff Institute for Physics, University of Heidelberg, Germany)

Description

The device presented at this work is a switch designed for compensating the skew which affects parallel data signal transmissions and for providing fault tolerance in large scale scalable systems, for instance used in trigger farms for high energy physics experiments. The SWIFT chip (SWItch for Fault Tolerance)is part of a cluster built around commercially components which has been inspired by the LHCb experiment. The skew is extremely important because it directly affects the sample window available to the receiver logic and either forces to use quality and expensive cables in order to minimize its effects or reduces the maximum signal transmission range or distance. This problem is handled by the deskewing circuitry at the SWIFT chip, which is able to match dynamically the signal transitions at the receiver link by adding an individual delay to each input signal in steps of 100 ps for LVDS signals up to 250 MHz. A 16-bit processor is implemented for processing tasks. SWIFT has been implemented in a 0.35 microns CMOS process, compensates dynamically skews of LVDS signals up to 250 MHz in steps of maximum 100 ps, and adds fault tolerance in the farm of PCs by allowing the bypassing of a failing compute node to which is attached.

Summary

In this work alternative techniques to minimize the effects of the skew in point-to-
point high frequency parallel data transmission over differential signaling are
presented. Novel methods of deskewing circuitries and comparison with existing
approaches were done. Based on the premises of minimizing the skew between the
parallel signals down to 100 ps, performing a self calibration of the skew in the
receiver link, and having the possibility to bypass a broken link adding fault
tolerance in order to do not disturb the data flow, an interface VLSI called SWIFT
compatible with any interconnection technology working at high frequency speeds is
designed in 0.35 µm CMOS process, implemented and satisfactory tested.

The architecture of the SWIFT chip developed is described. The bypass function in
SWIFT is implemented in a component which is snooping continuously the clock
signal, being received from the host (compute node, NIC, etc.) to which the chip is
attached. The deskew function is implemented by observing the timing transitions on
each data line relative to the received clock signal. Therefore the delays on each
line can be adjusted individually in order to optimize the sampling time relative
to the received clock. A fundamental part of the design is based on programmable
delay units capable to produce delays of 100 ps granularity. Since the skew which
must be compensated is a priori unknown and it changes randomly, a self calibration
skew circuitry is designed. An embedded processor is implemented in the chip for
adding versatility to the design. Analog and VHDL simulations of the entire placed
and routed chip are presented and discussed together with a description of the
mixed analogue and digital design flow of SWIFT, which was developed for the 0.35
µm CMOS process used. The results of the SWIFT testing and the comparison with
those existing from simulations are presented. The programmable delay units work as
expected producing delay steps of maximum 100 ps in a dynamic range of 2.75 ns. The
deskew function of SWIFT (dynamic and static mode) is verified and examples of skew
compensations down to 125 ps are shown. The bypass function of SWIFT is working
correctly. Extensive measurements results are presented, compared with simulated
ones, and discussed. The results show the feasibility of SWIFT under voltage
variations. The 16-bit processor is verified during the test procedure.

The chip implemented is used to theoretically improve the performances of a real
system as for example the trigger farm developed at KIP as a part of the data
acquisition system of a high energy physics experiment as the LHCb (Large Hadron
Collider Beauty) at CERN. It is feasible to significantly improve the performances
of such systems using the SWIFT chip as interface between the interconnect network
and the compute node of the farm. The positive results can in general be applied to
any point-to-point based system with ringlet as the basic element, which transmits
parallel signals between the hosts over differential signaling, and with large
amount of data transferred at high frequency speeds.

Presentation materials

Paper

paper