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Description
Summary
The readout electroncs of silicon detector modules are conventionally powered in
parallel, with a separate analog and digital power line and supply for each module.
This scheme offers the advantage of an independent voltage control over each module
and minimizes conductive interference between modules. The price to pay is the
large number of power cables, an increase of material in or near the tracking
volume, and the increased heat load through power losses in the cables.
An alternative approach –serial powering of modules from a single current source,
was proposed for application in the ATLAS pixel detector and prototyped with
encouraging results [1]. Serial powering of silicon detectors can dramatically
reduce the number of power cables in typical particle physics experiments. This is
particularly relevant in the context of a future SuperLHC silicon detector, which
will likely have five to ten times more channels than the current LHC detectors. In
addition to reducing the number of cables, serial powering can also lead to higher
power efficiency, defined as the ratio of power consumed by the readout electronics
to the total power delivered.
A study of the power efficiency of a serial powering scheme for silicon strip
detector modules was performed. Numerical results as a function of the number of
modules, supply voltage, and cable resistance are presented. It is shown that
serial powering results in a significantly higher power efficiency than a
conventional parallel powering scheme.
Tests with four ATLAS SCT silicon strip modules powered in series have been
performed using commercial voltage regulators and AC-coupled LVDS drivers. While we
follow the concept developed in [1], the hardware is different, most notably the
readout chip and the preamplifier input capacitance. The test results indicating
encouraging module performance are presented.
Two critical issues for the success of serial powering are the possibility of
increased noise through interference effects, and the danger of losing a chain of
serially connected modules in case of a single failure. Redundancy schemes and chip
specification issues related to serial powering will be discussed.
References:
[1] T. Stockmanns, P. Fischer, F. Hügging, I. Peric, Ö. Runolfsson, N. Wermes,
Nucl. Instr. and Meth. A 511, 174-179 (2003).
