Speaker
Description
Summary
The Delay25 is a 5 channel programmable delay line ASIC intended to be used in
timing distribution systems and for phase adjustment of signals in HEP experiments.
The ASIC consists of a master channel controlled by a Delay-Locked Loop (DLL) and
4 replica channels. It is able to delay asynchronous and uncorrelated digital
signals with a resolution of 0.5 ns. A signal can be delayed up to 32ns.
The master channel consists of a delay-locked loop that receives an external clock
reference. It locks to this signal guaranteeing a delay of 0.5 ns in each Delay
Element (DE) along the master delay line. This means that the delay on each DE of
the master delay line is independent of the process, temperature and supply voltage
being self calibrating.
Each delay line consists of 64 delay elements. The ASIC can operate with four
different reference frequencies: 32, 40, 64 and 80MHz. The control is made such
that along the line the total delay is exactly one clock period. Since each DE
should have 0.5 ns delay, the total number of delay elements used in the control
loop depends on the input signal frequency: 64 for 32 MHZ, 50 for 40 MHz, 32 for 64
MHz and 25 for 80 MHz.
The layout of the replica channels is made exactly the same as that of the DLL
delay line for good matching among the five delay lines. The replica delay lines
operate in open loop so the control voltage for each delay element on these lines
is the voltage that is generated by the DLL to control loop.
The ASIC has 6 internal registers that can be accessed by an I2C interface. Five of
these registers are used to program the delay of each channel. The other register
is used to program the operation mode and can also be used to initialise the DLL or
perform an ASIC reset through software.
The ASIC has five independent inputs and five independent outputs, one per channel.
The I/O levels can be configured through a dedicated pin to be either CMOS or LVDS
compatible.
The measured output jitter is below 10 ps (rms) for the master channel and below 20
ps (rms) for the replica channels. The integral non-linearity (difference between
the programmed delay and the measured delay) and the differential non-linearity
(difference from the expected delay in a certain tap and the measured delay for
that tap) are both below 50 ps (rms) for both the master and the replica channels.
The ASIC is manufactured in a 0.25 m CMOS standard technology using radiation
tolerant layout practices.
Measurement results will be presented focusing on the comparison of the performance
of the two I/O modes regarding output jitter, Integral and Differential non-
linearity, pulse distortion and crosstalk between channels.
