12–16 Sept 2005
Heidelberg
Europe/Zurich timezone

Design and performance of the front-end electronics of the LHCb Muon Detector

15 Sept 2005, 14:50
25m
Heidelberg

Heidelberg

Germany

Speaker

Dr walter Bonivento (INFN CAGLIARI, Italy)

Description

The system architecture of the front-end electronics of the LHCb Muon Detector, consisting of wire-chamber detectors and, for a small region, of triple-GEM detectors, is reviewed. The design of the front-end boards and of the ASD chip, the CARIOCA and the CARIOCA-GEM, are discussed in detail, together with the performances measured both with test benches in the lab and on chamber with radioactive sources and cosmic ray stands. The status of the production and the testing procedures of the 8,000 boards and the 24,000 chips, built with the 0.25mm radiation tolerant technology, will also be summarized.

Summary

The LHCb Muon system consists of five stations of detectors, M1 to M5, only the
first one lying before the calorimeters. Each station is radially segmented in
logical pads, which are the input cells to the level-0 Muon trigger, of four sizes,
R1 to R4.
Most of the system is builts with the wire-chamber technology while only M1-R1 is
built with the triple-GEM technology.
The front-end electronics of the Muon detector is based on two custom chips: the
CARIOCA (with a modified version for the GEM detector)and the DIALOG, both
designed with the 0.25mm radiation tolerant technology.
The CARIOCA is a fast (about 10ns peaking time) and low-noise (ENC=2500e-+45e-
*Cdet, where Cdet is the detector capacitance in pF, ranging from 15pF to 200pF in
the Muon system) amplifier-shaper-discriminator chip, with an active baseline
restoration circuit. A special version of it, named CARIOCA-GEM, was designed in
order to read-out the triple-GEM detector, with a modified shaping stage not
including the ion tail cancellation circuit.
The DIALOG chips takes care of the logical channel generation for the trigger and
of the interaction with the slow control system, i.e. threshold setting and front-
end monitoring.
The front-end boards house two CARIOCA chips and one DIALOG chips.
The experiment is now in the production phase of the front-end electronics,
including 8,000 boards and the 24,000 chips.
The front-end chips and boards are being extensively tested in the lab and their
interaction with grounding issues and power supply distribution of the chambers
studied in detail.

Author

Dr walter Bonivento (INFN CAGLIARI, Italy)

Co-authors

Dr Adriano Lai (INFN CAGLIARI, Italy) Mr Anatoli Katchouck (CERN, PNPI-Russia) Dr Burkhard Schmidt (CERN) Caterina Deplano (INFN CAGLIARI, Italy) Dr Danielle Moraes (CERN) Delia Rodriguez (CERN) Mr Felipe Vinci Dos Santos (CERN) Dr Francis Anghinolfi (CERN) Mr Nicolas Pelloux (CERN, Now at STMicroelectronics) Dr Pierre Jarron (CERN) Mr Rafael Nobrega (INFN Roma, Italy) Mr Sandro Cadeddu (INFN CAGLIARI, Italy) Mr Valerio Bocci (INFN Roma, Italy) Mr Vincenzo Deleo (INFN Cagliari) Dr Werner Riegler (CERN)

Presentation materials