Speaker
Description
Summary
The ALICE Transition Radiation Detector (TRD) consists of 6 layers
of drift chambers and radiators, arranged in a barrel geometry in
the central part of the ALICE heavy-ion experiment at LHC. It is
designed to track all charged particles and to perform electron
identification. It has the unique capability to provide a fast
electron trigger within 6 us after the collision. The TRD has more
than 1.2 million analog channels, which are digitized at 10 MSPS
with 10 bit resolution. The high number of channels implies that the
analog and most of the digital processing must be done within the
detector. The analog amplification and shaping is implemented as a
0.35 um AMS analog chip (PASA). The ADCs and the digital part of the
MCM are implemented as second chip in a 0.18 um UMC process. Both
chips build a low-cost Ball Grid Array (BGA) Multi Chip Module
(MCM), which looks like a commercial BGA chip. The ALICE TRD
detector uses about 65000 such MCMs.
The signals from the PASA are digitized by 21 10 bit ADCs at 10
MSPS. The ADC data pass through several filter stages: correction
for nonlinearity in PASA/ADC, pedestal and gain correction, tail
cancellation, crosstalk suppression.
The position within one time sample is reconstructed using the
charge sharing in a group of three adjacent pads. The about 20 space
points are subject to a straight line fit. Some part of the
calculations is done during the drift time, the rest
later in the four RISC CPUs.
The CPUs write the resulting track data as 32 bit word to the
parallel output of the chip. Within 600 ns all this information is
collected and shipped to the global tracking (GTU).
The root of the readout tree for a group of about 64 MCMs is
connected to a 2.4 Gbit optical transmitter. It combines the track
segments of the different detector layers into tracks within 2us.
The four CPUs have common quad ported data memory and individual
instruction memory blocks. In order to save power a global state
machine properly gates the LVDS cells and all clocks in the design.
A special designed slow control serial network is used
for all configuration of the chip (registers, memories). It runs at
24 Mbits/s and can address up to 126 chips in a daisy chain. An FPGA
board with RISC processor capable of running Linux with Ethernet
interface acts as a configuration master.
For the production of the TRAP and the MCM fully automated Wafer-
and MCM- testers were developed.
We have working chips and their designs are ready for production.
