Speaker
Description
Summary
The SPARC accelerator under construction at the Frascati National Laboratories
is dedicated to the realization of a Self Amplified Spontaneous Emission Free
Electron Laser (SASE FEL).
The SPARC control system is a multiprocessor system divided in three hierarchical
levels based on commercial and industrial PCs. The first consolle level implements
the operator interface, the second supervisor level manages the control system
shared memory and the third hardware level controls and monitors the machine.
The demonstrator of the reflective memory board for the communication between the
third and the second level PCs is presented.
Each third level reflective memory board has an associated 1 MByte memory zone in
the PCI memory space which is mirrored in a transparent way to the corresponding
second level reflective memory board.
The reflective memory board is implemented on a standard 32 bit x 66 MHz PCI
printed circuit board and can be logically divided in five building blocks: a
Master/Target PCI interface with DMA capabilities, a serdes controller with data
parity check, a DPRAM interface and reflective memory controller, a fiber optic
full-duplex high-speed link and a 1 MByte Synchronous Static Dual Port RAM.
The PCI interface, the serdes controller and the DPRAM interface were
implemented with an Altera Acex 1K 100 FPGA, for the DPRAM the 1 MByte Cypress
CY7C0853V was chosen and the high speed link was implemented using a Texas
Instruments TLK2501 serializer/deserializer circuit togherter with the Agilent
HFBR-5720AL SFP optical transceiver for a maximum throughput of 160 MByte/s
for each direction.
The reflective memory mechanism is implemented in a fully transparent way in
both directions. If a location in the PCI memory space of the board is modified
its data content is serialized from 32 to 16 bit and transmitted along the
optical fiber, togheter with an header indicating the destination memory address,
the memory transfer size and some control bits and a footer with a parity check.
The data received on the other side of the optical fiber are deserialized,
checked for transmission errors and written on the on-board DPRAM.
In this way the receiving PC has always an up-to-date copy of the 1 MByte PCI
memory space of the transmitting PC.
In case of error a retrasmission request message is sent to the transmitting PC
along the optical fiber.
The data from the transmitting PC are stored on the on-board DPRAM until they
are requested, thus reducing PCI bus traffic.
The DPRAM interface and reflective memory controller logic is able to check data
packet consistency too. In this way data corruption problems occurring when the
RX PC is reading a memory block during a data transfer from the high-speed link
can be avoided.
With the same mechanism used to mirror data from one PC to the other a message
passing and remote interrupt generation procedure is implemented too.
Two different low level drivers were realized: a driver for linux operating
system and a windows driver suitable to control the board with a LabView
program.
The board can be connected both in a point to point and ring configuration.
