Speaker
Description
Summary
Future experiments at the International Linear Collider (as well as at RHIC and
FAIR) call for highly granular, thin, radiation tolerant, fast and multi-layer
vertex detectors installed very close to the interaction region. As compared to
existing devices (CCDs, hybrid pixels), CMOS Monolithic Active Pixel Sensor (MAPS)
may offer an attractive trade-off between granularity, material budget, radiation
tolerance and read-out speed for high precision minimum ionizing particle (MIP)
tracking. This type of sensor integrates the sensing element and the processing
electronics on the same substrate. It is fabricated using standard CMOS processes
available through many commercial microelectronics foundries. The device ability to
provide charged particle tracking has been demonstrated on a series of MIMOSA
(Minimum Ionizing MOS Active sensor) chip prototypes [1].
The detection of charged particles with a CMOS sensor relies on a key element
made of an Nwell/P-substrate diode. The latter collects, through thermal diffusion,
the charge generated by the impinging particle in the thin, mostly undepleted,
silicon layer underneath the readout electronics (i.e. epitaxial layer). The charge
collected by each diode is directly converted to an electronic signal at the pixel
level. The particle tracking performance is limited by the leakage current of the
charge collecting diode, which increases with temperature and absorbed radiation
dose. As shown by existing MIMOSA prototypes, the sensors can be designed in order
to provide a sufficiently high signal-to-noise ratio (S/N) to allow for a spatial
resolution of about 1.5-2.5 µm and a detection efficiency in excess of 99%.
The signal processing (fully on-chip) micro-circuits is shared between the pixel
volume and the edge of the sensor. The ambitioned sensitivity and S/N performance
is best achieved by integrating a maximum of signal processing functionalities
inside the pixels. This is accomplished by integrating low noise amplifiers,
memories and correlated double sampling (CDS) circuits inside each pixel,
translating into a high charge-to-voltage conversion factor and reduced fixed
pattern noise. The required read-out speed is obtained by grouping the pixels in
short columns processed in parallel. Each column is equipped with an ADC and
sparsification micro-circuits integrated on the sensor edge. The design of the
latter is guided by minimal surface and power dissipation requirements (in order to
minimize the material budget). Various signal sensing and processing architectures
developed for future high precision vertex detectors (International Linear
Collider, STAR upgrade, CBM, etc …) will be presented. Their performances extracted
from tests realised with a 55Fe source and MIP beams (CERN-SPS) will be shown and
discussed. Besides this main issue, other current R&D topics will be addressed,
such as the thinning of the sensors to a few tens of micrometers, due to their thin
sensitive volume (typically ~10µm).
Finally, an outlook will be provided on the next prominent steps of the micro-
circuits design R&D.
