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Description
Summary
The paper presents the quality assurance system used for qualification of the
hybrids for the endcap silicon strip detector modules of the ATLAS Semiconductor
Tracker (SCT). The two endcap parts of the SCT detector comprise 1976 detector
modules. The required production scale ads new challenges to the quality assurance,
which are not present during development and prototyping phase. The hybrids
mentioned above are sophisticated electronic circuits used for readout double-sided
modules built of silicon strip detectors. The bare silicon chips are mounted onto a
flexible kapton printed circuit board, wrapped around a low mass carbon composite
mechanical support together with passive components. The chips glued and wire-
bonded on the hybrid are the twelve ABCD3T readout chips as well as the DORIC and
the VDC data transmission and optical link driver chips, providing in total 1536
readout channels, with their data transmitted over two independent optical links.
The electronics mounted on the hybrids provides extraction, amplification, and
discrimination of charge signals from silicon strip detectors, data derandomising
and data compression as well as transmission of data to an external data acquisition
system. The system design of the detector is fault-tolerant by design at many levels
and many of the components may fail without rendering large detector portion
unusable. The test chain of the components comprises the tests done for the
individual components (ASICs and PCBs), functionality tests and parameterisation
done after the assembly, and the burn-in test designed for catching possible infant
mortality in the ASICs and other components on the hybrids and ensure long-term
stability of the component. The hybrids were assembled in industry, where basic
functionality and reception tests were performed. Further QA tests were performed by
the SCT collaboration.
The test procedures were designed for maximising the rejection rate of faulty
components and, in the same time, minimising the testing time. The test routines are
composed of the series of visual test, electrical tests, and thermal cycling tests.
The mechanical defects and most of the assembly errors are detected by visual
inspection. The electrical functionality and parametric test use extensively the
testability function built into the ABCD3T front-end ASICs. Tests are performed
using the automated test software and custom-designed VME hardware, which makes it
possible to run the tests at high speed without overloading the control PC. In
addition to finding and marking the defected channels the analogue parameters of
each of the channels are measured and calibration factors are saved in the
conditional database for further use. The burn-in test is performed at elevated
temperature to speed up the development of possible infant mortality defects, and
the final characterisation of the parameters is done at the nominal working
temperature of the ATLAS SCT.
The QA testing of endcap hybrids was conducted at three sites: the AGH University of
Science and Technology in Krakow, the Freiburg University in Germany and the
Rutherford Appleton Laboratory in the UK. In the paper we will present the QA
procedures, example of test results and statistical summary for the entire
production.
