Speaker
Description
Summary
The LHC bunch clock frequency of 40 MHz is transmitted to the experiments via a
network of optical fibres which is partly based on non-phase-stabilized fibres. In
the case of the LHCb experiment the non-phase stabilized distance is about 4.6km.
In LHCb the bunch clock is locally distributed by the Timing and Fast Control
system to all the detector front-end electronics where it is used to sample the
detector signals. In order to sample the detector signals, which typically have a
maximum plateau of a nanosecond, at the optimum point, the timing system provides
several means of making a complete timing alignment at the level of 50ps. Since the
LHC fills are expected to last for more than ten hours, it is of extreme importance
that the phase of the LHC clock remains stable with respect to the bunch arrival
times.
However, several effects such as temperature variations influence the phase.
Measurements show that the time drift on the transmission fibres could be as large
as 200ps over a period of 24 hours, and up to 8ns have been observed over a period
of a year. Clearly the phase must be monitored and regular timing alignments must
be performed.
In order to monitor the bunch arrival times with respect to the clock a special
Button Electrode beam pickup will be installed 180m away from the interaction
points on each side. Since the pulses of the four buttons of each pickup will be
summed, the signal per crossing becomes independent of the position of the beam and
thus also allows measuring the currents of the bunches. This is of high interest
since the LHC bunch structure can be monitored and the bunch currents can be
correlated with the actual physics triggers.
The current paper proposes a beam phase and intensity acquisition board (BPIM)
capable of performing the two measurements per bunch crossing. The analogue unit of
the board consists of a separate circuit for the phase measurement and the
intensity measurement. Since the shape and the amplitude of the pulse will vary,
the phase measurement circuit contains a special pulse detect circuit which is
independents of the shape, and the intensity measurement circuit contains a
programmable gain amplifier. The digital processing of the board is based on an
FPGA which performs response linearization, averaging and histogramming in the
memory of the FPGA of the measurements. The control interface is based on an
embedded Credit-Card-sized PC from Digital Logic. The controller has Ethernet and
is one of the standard interfaces to the Experiment Control System in LHCb. The
control of the analogue circuits, such as gains and thresholds, is handled through
the FPGA. In addition to reading out the measurements via the control interface,
they are also output on the front-panel of the board at 40MHz with LVDS. The latter
allows directly interfacing the board to the Timing and Fast Control system in
order to add the bunch current information to the data of each event.
The board is in development. A first full design has been made and simulated. One
of the authors* has also implemented and tested the design in the context of an
intensity monitor for the CERN PS accelerator.
(* G. Kasprowicz)
