Speaker
Description
Summary
The FPGA Virtual File System (FPGA VFS) is a technology based around the idea of
FPGA Dynamic Reconfiguration. It provides accessibility of the FPGA configuration
data of Xilinx Virtex devices on different levels of abstraction. We are using the
FPGA VFS to improve various aspects of ALICE electronics, in particular for the
TPC, RCU, TRD and GTU.
As reported previously, we have performed radiation tolerance experiments with
Xilinx Virtex-II Pro FPGAs, using the FPGA VFS to identify and repair single-event
upsets in the configuration memory. The results of this initial work formed the
basis for the redesign of the RCU, leading to a system with a higher radiation
tolerance and significantly improved system availability. We will give a brief
summary of the key technologies and system requirements to built such a system.
More recently, we have been investigating other applications of the FPGA VFS for
ALICE electronics. In these applications, the Virtual File System acts as the
middleman between the user (or engineer) and the hardware by taking care of the
details of FPGA reconfiguration and providing the necessary functionality at the
required level of abstraction.
Of particular interest are the following two: in-vivo replacement (reloading) of
functional modules, and in-system, non-invasive FPGA debugging.
Reloading of functional modules is one of the key ideas of FPGA Dynamic
Reconfiguration. In ALICE electronics, it can improve the overall performance of
the system. It does so by enabling the system to adapt to changing requirements,
and it allows to fit more functionality into smaller parts, thus helping keep the
system within power restrictions. To give some examples: using different algorithms
when observing different trigger conditions, dynamically changing the routing or
processing for faulty modules, loading I2C diagnostics modules depending on pecific
error conditions etc. are all possible using this technology.
Debugging of the in-system FPGA is an idea resulting from the capability of the
FPGA Virtual File System to represent all components of the FPGA in a user
configurable hierarchy. In particular, it can present the states of the flip-flops
and memories using the naming from the HDL source,
i.e. “/module_name/component_name/register_name”. It can also be used to
reconfigure the clocks to allow single-stepping of the FPGA.
Combining these features, we get two of the three basic functionalities of any
software debugger – inspection of memories and single-stepping. In contrast to
other approaches to FPGA debugging, the Virtual File System does not
require modifications to the existing design, thus preserving the original system.
The third basic functionality, the ability to set break points, is not currently
part of our work, but certainly not impossible achieve.
We will report about the details of both concepts, as well as the status of their
practical implementation in ALICE.
