11th Workshop on Electronics for LHC and future Experiments

Session

Plenary Session P2

P2

13 Sept 2005, 09:00

Heidelberg

113. CMOS Technology Characterization for analog/RF application

Dr Ehrenfried Seebacher (Austriamicrosystems)

13/09/2005, 09:00

We discuss state of the art and new developments for the characterization of CMOS technologies. In the first chapter the most important issues of MOS transistor modeling will be shown. Topics like AC/DC modeling, noise modeling and temperature modeling for the MOS transistor will be explained. State of the art MOS transistor models like the BSIM3 and BSIM4 models as well as the...

11. 0.13 um CMOS technologies for analog front-end circuits in LHC detector upgrades

Dr Massimo Manghisoni (Università degli Studi di Bergamo)

13/09/2005, 09:45

Oral

Deep submicron CMOS technologies are widely used for the implementation of low noise front-end electronics in various detector applications. In this field the designers’ effort is presently focused on 0.13 micron technologies. This work presents the results of noise measurements carried out on CMOS devices in 0.13 um commercial processes from different foundries. The study also...

58. Operational Experience with the CDF Run II Silicon detector

Dr Marcel Stanitzki (Yale University)

13/09/2005, 10:10

Oral

The CDF Silicon Vertex detector consists of three subdetectors: SVX-II, ISL and L00. Altogether it consists of 8 layers of Silicon with more than 750000 readout channels. This detector is essential for CDF's high precision tracking and is vital for the forward tracking capabilities and the identification of heavy flavor decays. After four years of data taking in Run-II and a delivered...