Detector Seminar

Layout techniques to enhance the radiation tolerance of standard CMOS technologies demonstrated on a pixel readout chip

Name: Layout techniques to enhance the radiation tolerance of standard CMOS technologies demonstrated on a pixel readout chip
Start: 1998-10-19T00:00:00+02:00
End: 1998-10-19T00:15:00+02:00
Location: CERN

by W. Snoeys (CERN/EP)

Monday 19 Oct 1998, 00:00 → 00:15 Europe/Zurich

CERN

Description

Two new pixel readout prototypes have been developed at CERN for application in the Alice experiment. he radiation tolerance of these full mixed mode analog digital circuits implemented in commercial CMOS technologies has been enhanced by modifying the circuit layout. The first circuit implemented in a 0.5 mm CMOS technology tolerated up to about 1.7 Mrad in a particle beam. The second one was designed in a 0.25 mm CMOS technology and remained functional up to a 30 Mrad X-ray dose. In the presentation the layout techniques will be explained and their effectiveness demonstrated on various irradiation measurements on individual transistors and on the pixel readout prototypes. Implications of such a layout approach on the circuit design will also be discussed.

Organiser(s): Rui Ribeiro EP Div