OTHER SEMINARS - Reduction of 1/f noise in MOS transistors

by Professor Bram Nauta (University of Twente, Enschede, The Netherlands)

Wednesday 6 Dec 2000, 14:30 → 15:30 Europe/Zurich

13/2-005 (CERN)

Switched Biasing is a new a technique for reducing the 1/f noise in MOSFETS. Conventional techniques, such as chopping or correlated double sampling, reduce the effect of 1/f noise in electronic circuits, whereas the Switched Biasing technique reduces the 1/f noise itself. It exploits an intriguing physical effect: cycling a MOS transistor from strong inversion to accumulation reduces its 1/f noise. In fact the transistor 'forgets' its past and thus these low-frequency noise components. This effect is important, especially in RF circuits where 1/f noise is often being upconverted, and is thus a serious problem. The history of the (re)discovery of the effect and the main experimental results obtained so far will be reviewed. About the speaker: Professor Bram Nauta/ University of Twente/NL In 1991 he joined the Mixed-Signal Circuits and Systems Department of Philips Research where he worked on high speed AD converters. From 1994 he led a research group in the same department, working on 'analog key modules'. This included amplifiers, filters, PLL's, voltage regulators, line drivers, reference circuits, substrate interference etc., mainly in CMOS technology. In 1998 he returned to the University of Twente, as full professor heading the department of IC Design in the department of Electrical Engineering. He also heads the IC Design Group in the MESA research Institute. His current research interest is analog CMOS circuits for transceivers. His Ph.D. thesis was published as a book: Analog CMOS Filters for Very High Frequencies, Boston, MA, Kluwer, 1993. He holds 8 patents in circuit design and he received the 'Shell Study Tour Award' for his Ph.D. Work. In 1997 he became Associate Editor of IEEE Transactions on Circuits and Systems -II; Analog and Digital Signal Processing. In 1998 he served as Guest Editor for IEEE Journal of Solid-State Circuits.

Organiser(s): P. Jarron/EP