Speaker
Mr
Michael Laverty
(TRIUMF)
Description
An optimized digital phase detector for a 106 MHz superconducting cavity was
designed using state machine logic. Transitions of the feedback and reference
inputs trigger corresponding changes in the state of the detector. The state
machine has been implemented using a high speed Xilinx field programmable gate
array. The resulting design incorporates two phase detectors (one for the phase
loop and one for the tuning loop), two frequency counters, and a subractor. The
counters and subtractor are used to determine the frequency error for initial
tuning of the cavity. The design and some initial test results are presented.
Author
Mr
Michael Laverty
(TRIUMF)
Co-authors
Dr
Ken Fong
(TRIUMF)
Dr
Shuyao Fang
(TRIUMF)
