Total Ionising Dose (TID) at levels beyond 100Mrad clearly affects the performance of transistors in the 65nm CMOS technology chosen for LHC upgrades. However, measurements performed in different Institutes in the last 2 years have revealed a complex phenomenology where the radiation damage depends on transistors’ size, applied bias and temperature (during both exposure and post-irradiation annealing). Some of the gathered observations are difficult to explain on the basis of the present knowledge on radiation effects and question the validity of the standard qualification procedures for CMOS technologies. This presentation uses the measurements performed at the CERN X-ray irradiation facility in the last 10 months to try giving the audience a comprehensible view of the radiation effects.
