Evaluation of new design and verification methodologies for FPGA design

by Michal Husejko (CERN)

Tuesday 8 Dec 2015, 09:00 → 10:00 Europe/Zurich

13/2-005 (CERN)

Over the last few years, IT has been investigating new FPGA design and verification tools and methodologies. These claim to be able to lead higher productivity and/or shorter design time. We decided that it would be useful to investigate again how the latest advances could be applicable to the CERN environment.

Today's seminar will cover High Level Synthesis with particular focus on Xilinx Vivado HLS. It will include experience on its use for a typical CERN project.

Content:

• A brief history of HLS tools and previous CERN investigations
• Overview of Vivado HLS tool
• Case study - CMS ECAL Data Concentrator Card (DCC)
• Conclusions

mhusejko_PH_ESE_HLS_v3.pdf