Single Event Upsets mitigation techniques (TMRG tool)

by Szymon Kulis (CERN)

Tuesday 12 Apr 2016, 09:00 → 10:00 Europe/Zurich

13/2-005 (CERN)

Single Event Upsets (SEU) are a major concern for integrated circuits exposed to radiation, especially for circuits fabricated in modern deep sub-micron technologies. For reliable detector operation in environments such as the LHC it is necessary to protect the logic from radiation induced upsets. There have been several techniques proposed in order to protect the circuit against SEU. Virtually all techniques rely on data redundancy. It is assumed that if the information is stored in several places (circuit nodes), it can be properly reconstructed even if some of these nodes are disturbed. Among the SEU hardening techniques, some are based on hardening standard cells. Others address the problem on a system level, by utilizing error-correcting coding (ECC), temporal redundancy, or Triple Module Redundancy (TMR). The seminar covers basic methods of protecting data against SEU. It will cover at length the Triple Module Redundancy Generator (TMRG) tool developed at CERN. The purpose of the TMRG tool is to automatize process of triplicating digital circuits freeing the designer from introducing the TMR code at the implementation stage. It helps to ensure that triplicated logic is maintained through the design process from RTL down to place and route. Finally, the tool provides an uniform mechanism to introduce SEU and SET in gate level transient simulations for final verification.

tmrg_skulis_ep_ese.pdf