Speaker
Description
Summary
Following a study made in 2009 to implement the GBT SERDES in FPGAs, the GBT-FPGA project was launched. Its main goal is to provide a unified GBT core for multiple users and different FPGAs in order to allow communicating with the GBTx. The VHDL-based IP is used for the upgrade of the LHC’s experiments DAQ and timing systems as well as the emulation of GBTx chip for test purposes. It provides two types of implementation for the transmitter and the receiver (“Standard” and “Latency-optimized”) as well as two encoding schemes supported by the GBTx serializer/deserializer ASIC (“GBT-Frame” (Reed-Salomon) and “Wide bus”). The package also includes some example designs for the most common FPGA development kits.
The poster focuses on the main release foreseen for June 2016 including the slow control. This feature is used to monitor/control the front-end electronics. It allows writing/reading GBTx internal registers (Internal Control) to configure the chip and get different status as well as communicating with SCAs (External Control). One GBT link can be used to control up to 21 SCAs. Different types of commands will be implemented to use all the available interfaces (I2C, JTAG, GPIO, SPI …). The poster also report a status on the GBT-FPGA project with the descriptions of the latest releases (support of the latest development tools, bug corrections …) and the plans for the future versions (new FPGAs to be supported).
