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ACES 2016 - Fifth Common ATLAS CMS Electronics Workshop for LHC Upgrades

7–10 Mar 2016
CERN
Europe/Zurich timezone
There is a live webcast for this event.

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Session

Poster

8 Mar 2016, 16:00
30/7-018 - Kjell Johnsen Auditorium (CERN)

30/7-018 - Kjell Johnsen Auditorium

CERN

Building 30/7-018 CH - 1211 Geneva 23
190
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Presentation materials

ACES2016.pdf
ACES 2016 - VMM for MDTs.pdf
ACES Poster - UTD ADC.pdf
ACES Poster - UTD ADC.pptx
PFernandez_Poster_ACES2016.pdf
Poster_ACES2016_v2.0.pdf
Poster_ACES2016_zeloufi_corrigé.pdf
  1. 1. The Versatile Link Demontrator Board (VLDB)
    Raul Martin Lesma (Centro de Investigaciones Energ. Medioambientales y Tecn. - (ES)
    08/03/2016, 16:00
    Poster
    The Versatile Link Demonstrator Board (VLDB) is the evaluation kit for the Radiation Hard Optical Link ecosystem, which provides a 4.8 Gbps data transfer link for communication between front-end and back-end of the experiments. It gathers the Versatile Link main radiation hard custom ASICs: GBTx, GBT-SCA and VTRx/VTTx plus the FeastMP, a radiation hard in-house designed DCDC. This board is the...
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  2. 60. Rad-Hard Vertical JFET switch for the HV-MUX system of the ATLAS upgrade ITk
    Dr Pablo Fernandez-Martinez (Instituto de Microelectrónica de Barcelona (IMB-CNM,CSIC))
    08/03/2016, 16:02
    Poster
    This work presents a new silicon vertical JFET transistor, based on a trenched technology developed at the IMB-CNM, to be used as switch for the High-Voltage power distribution in the ATLAS upgrade Inner Tracker. After a thorough optimization work, performed by TCAD simulations, selected designs have been chosen for device fabrication at the IMB-CNM clean room. The first prototypes have been...
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  3. 59. Status update and future plans for the GBT-FPGA project at CERN
    Julian Maxime Mendez (CERN)
    08/03/2016, 16:05
    Poster
    The poster focuses on the main release foreseen for June 2016 including the slow control. This feature is used to monitor/control the front-end electronics. It allows configuring the GBTx and communicating with the SCA. One GBT link can be used to control up to 21 SCAs. Different types of commands will be implemented to use all the available interfaces. The poster also report a status on the...
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  4. 61. The use of the ATLAS Small Wheel front end Electronics for the HL-LHC MDT upgrade
    Venetios Polychronakos (Brookhaven National Laboratory (US))
    08/03/2016, 16:07
    Poster
    The use of the ATLAS New Small Wheel electronics readout architecture for the trigger and readout of the Monitored Drift Tube (MDT) detectors of the ATLAS Muon Spectrometer in the HL-KHC is proposed. In the core of the proposal is the VMM, the front end ASIC that will be used for bothe Micromegas and sTGC detectors.
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  5. 62. Preliminary Experimental Results of A 14-bit Split-SAR ADC for ATLAS LAr Phase-II Upgrade
    Dr Yun Chiu (Department of Electrical Engineering, University of Texas at Dallas)
    08/03/2016, 16:09
    Poster
    Preliminary experimental results of a 14-bit split-SAR ADC prototype implemented in 65-nm CMOS are reported. Inherent architectural redundancy and the newly proposed SEE-detection circuitry constitute two prominent features of this work for efficient SEE detection and correction (to be experimentally verified). With FIB and foreground calibration, the prototype ADC measured a 74.6-dB peak SNDR...
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  6. 63. Timepix detector network for luminosity monitoring and characterization of the radiation fields within the ATLAS cavern
    Benedikt Ludwig Bergmann (Czech Technical University (CZ))
    08/03/2016, 16:11
    Poster
    A network of 13 Timepix detector based devices consisting of two sensitive sensors interlaced by neutron converter layers was installed at different locations in the ATLAS detector cavern during the recent shut-down. In this poster, we present the calibration measurements (photons, neutrons and ions) of the individual devices, their positions within the ATLAS cavern, the data acquisition...
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  7. 64. Design of low power 12bit 40MSPS SAR ADCs with a redundancy algorithm and digital calibration for high dynamic range calorimeter readout
    Daniel Dzahini (LPSC/IN2P3)
    08/03/2016, 16:13
    Poster
    We present two SAR ADCs using a generalized redundant search algorithm and offering the flexibility to relax the requirements on the DAC settling time. Two more bits of redundancy allow also a digital calibration, based on a code density analysis to compensate the capacitors mismatching effects. A monotonic switching algorithm is used for these prototypes saving about 70% of dynamic power...
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  8. 65. The intelligent, FPGA-based event builder and Data Acquisition System of COMPASS – an exemplary system for the future?
    Dominik Steffen (Technische Universitaet Muenchen (DE))
    08/03/2016, 16:15
    Poster
    Using FPGA-technology for event building tasks in high-energy physics experiments reduces costs and increases reliability of DAQ-systems. In 2015, COMPASS experiment at CERN’s SPS commissioned a novel, intelligent, FPGA- based DAQ (iFDAQ) in which event building is performed by FPGAs. The highly scalable system is designed to cope with an on-spill data rate of 1.5 GB/s and sustained data...
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  9. 66. ATLAS LAr Phase II upgrade of the Front End Electronics
    Mitchell Franck Newcomer (University of Pennsylvania (US))
    08/03/2016, 16:17
    Poster
    The Phase II upgrade of the ATLAS Liquid Argon detector includes a 17 bit dynamic range front end amplifier with a two or three gain multi‐pole shaper employing CR‐(RC)n shaping. Each gain stage of the shaper will be followed by a 40Msps, 14b dynamic range, 12‐13b ENOB digitizer, serializer and fiber optic driver. A study is underway to see if a single technology (65nm or 130nm CMOS) will be...
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