the project will bring together high performance pattern recognition technologies
and 3D chip integration. This allows to increase the number of pattern stored in
the memory and a reduction of power dissipation.
The main goals of this project will be:
Designing and producing of innovative cost effective and low energy associative
memory chip to provide an integrated circuits with high performance in term of
processing capability, efficiency and reliability.
Using innovative 3D chip technologies to stack in one chip many layers of active silicon
connected by Trough Silicon Vias (TGVs).
The main technological objectives will be:
Development of a new Associative Memory chip in aggressive technology nodes (28 nm).
Design associative memory core using ultra low power technology to reduce the power consumption.
Design of novel computing architectures in the 3D domain.
The project will take advantage of the state of the art 3D asic design and will open to new breakthroughs in the design, implementation
and testing of new associative memory chip requiring the control of mixed
criticalities (i.e. power dissipation, clock and signal distribution) opening multifaceted applications in industry
(i.e. control of industrial processes), engineering (i.e. real-time context aware
vehicles), health-care (i.e. dynamic diagnostics), etc.
Direct Applications and Industrial end users:
- High energy physics: trigger system.
- Medical Industry: Real time analysis of medical imaging data.
- Robotics and computer vision.