Speakers
Mr
Eric Oberla
(University of Chicago)Mr
Herve Grabas
(University of Chicago)
Description
In the scope of time of flight measurements at a scale of few pico-seconds, a CMOS fast sampler chip is being developed in 130nm CMOS technology. It includes a 10-20GS/s timing generator lockable on a 40-80 MHz clock and four channels of 256 sampling cells able to record up to of 25ns of analog information. The sampling process is continuously running and is stopped upon an external trigger. Each sampling cell is integrated with a comparator allowing a 12-bit analog-to-digital conversion. Measurements results are presented in terms of sampling rate, analog bandwidth, dynamic range, signal-to-noise ratio, linearity, analog-to-digital conversion and power performance.
Summary (Additional text describing your work. Can be pasted here or give an URL to a PDF document):
http://edg.uchicago.edu/papers/
Primary authors
Mr
Eric Oberla
(University of Chicago)
Mr
Herve Grabas
(University of Chicago)
Dr
Jean-Francois Genat
(University of Chicago)
Co-authors
Mr
Fukun Tang
(University of Chicago)
Prof.
Gary Varner
(University of Hawaii)
Prof.
Henry Frisch
(University of Chicago)
Dr
Kurtis Nishimura
(University of Hawaii)
Mr
Larry Ruckman
(University of Hawaii)
Ms
Mary Heintz
(University of Chicago)
Mr
Mircea Bogdan
(University of Chicago)
Mr
Samuel Meehan
(University of Chicago)
